Attention is currently required from: Amanda Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj.
Subrata Banik has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83549?usp=email )
Change subject: mainboard/google/brya/variants/orisa: Change board strap memory config
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83549/comment/842a485c_ff9a7e14?us… :
PS1, Line 7: mainboard
mb
https://review.coreboot.org/c/coreboot/+/83549/comment/c69829f9_9c7042b5?us… :
PS1, Line 17: None
There should be atleast build test.
File src/mainboard/google/brya/variants/orisa/memory.c:
https://review.coreboot.org/c/coreboot/+/83549/comment/80b950da_076922f9?us… :
PS1, Line 90: NC
this is not needed
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83548?usp=email )
Change subject: mb/google/brya/var/trulo: Add TCSS port descriptions
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mb/google/brya/var/trulo: Add TCSS port descriptions
This patch adds descriptions for TCSS port, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime
with port definitions, locations, and type information.
Additionally, implement the TCSS PMC MUX programming.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/83548/1
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index a23a20e..73106e92 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -20,8 +20,28 @@
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 (MLB)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 (DB)
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+ # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
+ # Bit 2 - C1 has a redriver which does SBU muxing.
+ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
+ register "tcss_aux_ori" = "0"
+
device domain 0 on
device ref igpu on end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port1 on end
+ end
+ end
+ end
+ end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
@@ -87,8 +107,20 @@
device ref ufs on end
device ref pch_espi on
chip ec/google/chromeec
+ use conn0 as mux_conn[0]
device pnp 0c09.0 on end
end
end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port5 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ end
+ end
+ end
end
end
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