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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/common/vboot/vbnv_cmos.c:
https://review.coreboot.org/c/coreboot/+/83495/comment/f58ae2b8_0567961b?us… :
PS4, Line 16: cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);
> GOOGLE_DEWATT, GOOGLE_GUYBRUSH, GOOGLE_NIPPERKIN builds failed with "stack overlaps the previous reg […]
As I am digging about it a little bit, it seems the error is observed only with clang and not gcc. Is anything special to be done for PSP Verstage with clang?
Also the issue is happening only in MonkeyIsland and not on Zork(prior generation) or Skyrim(later generation).
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Change subject: mb/google/brya/var/trulo: Populate DRAM configuration parameters
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83541/comment/d079a2b8_db0c89f9?us… :
PS1, Line 15: - SPD Index
> It’d be great if you documented the source for the values you used.
Acknowledged
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Change subject: mb/google/brya/var/trulo: Populate DRAM configuration parameters
......................................................................
mb/google/brya/var/trulo: Populate DRAM configuration parameters
This patch adds key DRAM configuration parameters as below:
- Rcomp
- DQ byte map
- DQS CPU<>DRAM map
- ECT
- CCC Mapping
- SPD Index
Source: Trulo Schematics Rev0.5 (dated June'24)
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/brya/variants/trulo/Makefile.mk
A src/mainboard/google/brya/variants/trulo/memory.c
2 files changed, 113 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/83541/2
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Change subject: mb/google/brya/var/trulo: Add LPDDR5 DRAM (MT62F512M32D2DR-031)
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83539/comment/28e77bde_6712853b?us… :
PS1, Line 7: Lp5 DRAM
> This spelling does not have any hits on the Web for me. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83539/comment/65ad8680_21f22dc8?us… :
PS1, Line 9: MT
> Note to self: That is Micron Technology
Acknowledged
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Change subject: mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT
......................................................................
Patch Set 5: Code-Review+1
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Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: azalia: Get rid of "return {-1,0}
......................................................................
azalia: Get rid of "return {-1,0}
Use 'enum cb_err' instead of {-1,0}.
Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/device/azalia_device.c
M src/include/device/azalia_device.h
M src/soc/intel/common/hda_verb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/lynxpoint/hda_verb.c
9 files changed, 36 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/83503/4
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Hello Julius Werner, build bot (Jenkins),
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The following approvals got outdated and were removed:
Code-Review-1 by Julius Werner, Verified+1 by build bot (Jenkins)
Change subject: azalia: Get rid of "return {-1,0}
......................................................................
azalia: Get rid of "return {-1,0}
Use 'enum cb_err' instead of {-1,0}.
Change-Id: Icea33ea3e6a5e3c7bbfedc29045026cd722ac23e
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/device/azalia_device.c
M src/include/device/azalia_device.h
M src/soc/intel/common/hda_verb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/lynxpoint/hda_verb.c
9 files changed, 36 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/83503/3
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Change subject: mb/google/brya/var/trulo: Populate DRAM configuration parameters
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83541/comment/70e91a43_070aa00b?us… :
PS1, Line 15: - SPD Index
It’d be great if you documented the source for the values you used.
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