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[XS] Change in coreboot[main]: device/pci_ids: Remove unused Intel UFS device IDs
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83519?usp=email
) Change subject: device/pci_ids: Remove unused Intel UFS device IDs ...................................................................... device/pci_ids: Remove unused Intel UFS device IDs This patch removes the PCI device IDs for Intel LNL and PTL UFS devices from `pci_ids.h` as they appear to be unused in the codebase. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ic795dd2e83c361a2aa04267d4663cf6bb9a755e2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83519
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/include/device/pci_ids.h 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: Angel Pons: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e18a2fb..27cedd9 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4725,10 +4725,6 @@ #define PCI_DID_INTEL_JSP_EMMC 0x4dc4 #define PCI_DID_INTEL_ADP_EMMC 0x54c4 -/* Intel UFS device Ids */ -#define PCI_DID_INTEL_LNL_UFS 0xa847 -#define PCI_DID_INTEL_PTL_UFS 0xe447 - /* Intel Thunderbolt device Ids */ #define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23 #define PCI_DID_INTEL_TGL_TBT_RP1 0x9a25 -- To view, visit
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic795dd2e83c361a2aa04267d4663cf6bb9a755e2 Gerrit-Change-Number: 83519 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[XS] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for XDCI
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83518?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for XDCI ...................................................................... device/pci_ids: Add new Intel PTL device IDs for XDCI This patch adds new XDCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XDCI driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused TCSS XDCI PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I51196401904e2402ac7669fa852a541bb7c2d453 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83518
Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/xdci/xdci.c 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: Angel Pons: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 445658f..e18a2fb 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4704,7 +4704,8 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 -#define PCI_DID_INTEL_PTL_TCSS_XDCI 0xe432 +#define PCI_DID_INTEL_PTL_H_XDCI 0xe47e +#define PCI_DID_INTEL_PTL_U_H_XDCI 0xe37e /* Intel SD device Ids */ #define PCI_DID_INTEL_LPT_LP_SD 0x9c35 diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 7ee2dbb..86625da 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -28,6 +28,8 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_H_XDCI, + PCI_DID_INTEL_PTL_U_H_XDCI, PCI_DID_INTEL_MTL_XDCI, PCI_DID_INTEL_APL_XDCI, PCI_DID_INTEL_CNL_LP_XDCI, -- To view, visit
https://review.coreboot.org/c/coreboot/+/83518?usp=email
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51196401904e2402ac7669fa852a541bb7c2d453 Gerrit-Change-Number: 83518 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[XS] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for CSE0
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83517?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for CSE0 ...................................................................... device/pci_ids: Add new Intel PTL device IDs for CSE0 This patch adds new CSE0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CSE0 driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused CSE1-3 PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83517
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cse/cse.c 2 files changed, 4 insertions(+), 5 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 716f386..445658f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4679,10 +4679,8 @@ #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 #define PCI_DID_INTEL_LNL_CSE0 0xa870 -#define PCI_DID_INTEL_PTL_CSE0 0xe470 -#define PCI_DID_INTEL_PTL_CSE1 0xe471 -#define PCI_DID_INTEL_PTL_CSE2 0xe474 -#define PCI_DID_INTEL_PTL_CSE3 0xe475 +#define PCI_DID_INTEL_PTL_H_CSE0 0xe470 +#define PCI_DID_INTEL_PTL_U_H_CSE0 0xe370 /* Intel XDCI device Ids */ #define PCI_DID_INTEL_APL_XDCI 0x5aaa diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ed07f69..6389044 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1479,7 +1479,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_CSE0, + PCI_DID_INTEL_PTL_H_CSE0, + PCI_DID_INTEL_PTL_U_H_CSE0, PCI_DID_INTEL_LNL_CSE0, PCI_DID_INTEL_MTL_CSE0, PCI_DID_INTEL_APL_CSE0, -- To view, visit
https://review.coreboot.org/c/coreboot/+/83517?usp=email
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b Gerrit-Change-Number: 83517 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[M] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for Audio
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83516?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for Audio ...................................................................... device/pci_ids: Add new Intel PTL device IDs for Audio This patch adds new Audio (HDA/DSP) PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the Audio driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I3c9e420a6ae19d00fb5510c99d4c219dc43ad3c0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83516
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/hda/hda.c 3 files changed, 48 insertions(+), 24 deletions(-) Approvals: Angel Pons: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index dac7508..716f386 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4617,14 +4617,22 @@ #define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e #define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f -#define PCI_DID_INTEL_PTL_AUDIO_1 0xe428 -#define PCI_DID_INTEL_PTL_AUDIO_2 0xe429 -#define PCI_DID_INTEL_PTL_AUDIO_3 0xe42a -#define PCI_DID_INTEL_PTL_AUDIO_4 0xe42b -#define PCI_DID_INTEL_PTL_AUDIO_5 0xe42c -#define PCI_DID_INTEL_PTL_AUDIO_6 0xe42d -#define PCI_DID_INTEL_PTL_AUDIO_7 0xe42e -#define PCI_DID_INTEL_PTL_AUDIO_8 0xe42f +#define PCI_DID_INTEL_PTL_H_AUDIO_1 0xe428 +#define PCI_DID_INTEL_PTL_H_AUDIO_2 0xe429 +#define PCI_DID_INTEL_PTL_H_AUDIO_3 0xe42a +#define PCI_DID_INTEL_PTL_H_AUDIO_4 0xe42b +#define PCI_DID_INTEL_PTL_H_AUDIO_5 0xe42c +#define PCI_DID_INTEL_PTL_H_AUDIO_6 0xe42d +#define PCI_DID_INTEL_PTL_H_AUDIO_7 0xe42e +#define PCI_DID_INTEL_PTL_H_AUDIO_8 0xe42f +#define PCI_DID_INTEL_PTL_U_H_AUDIO_1 0xe328 +#define PCI_DID_INTEL_PTL_U_H_AUDIO_2 0xe329 +#define PCI_DID_INTEL_PTL_U_H_AUDIO_3 0xe32a +#define PCI_DID_INTEL_PTL_U_H_AUDIO_4 0xe32b +#define PCI_DID_INTEL_PTL_U_H_AUDIO_5 0xe32c +#define PCI_DID_INTEL_PTL_U_H_AUDIO_6 0xe32d +#define PCI_DID_INTEL_PTL_U_H_AUDIO_7 0xe32e +#define PCI_DID_INTEL_PTL_U_H_AUDIO_8 0xe32f /* Intel HECI/ME device Ids */ #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 7e8322e..ab0e116 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -13,14 +13,22 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_AUDIO_1, - PCI_DID_INTEL_PTL_AUDIO_2, - PCI_DID_INTEL_PTL_AUDIO_3, - PCI_DID_INTEL_PTL_AUDIO_4, - PCI_DID_INTEL_PTL_AUDIO_5, - PCI_DID_INTEL_PTL_AUDIO_6, - PCI_DID_INTEL_PTL_AUDIO_7, - PCI_DID_INTEL_PTL_AUDIO_8, + PCI_DID_INTEL_PTL_H_AUDIO_1, + PCI_DID_INTEL_PTL_H_AUDIO_2, + PCI_DID_INTEL_PTL_H_AUDIO_3, + PCI_DID_INTEL_PTL_H_AUDIO_4, + PCI_DID_INTEL_PTL_H_AUDIO_5, + PCI_DID_INTEL_PTL_H_AUDIO_6, + PCI_DID_INTEL_PTL_H_AUDIO_7, + PCI_DID_INTEL_PTL_H_AUDIO_8, + PCI_DID_INTEL_PTL_U_H_AUDIO_1, + PCI_DID_INTEL_PTL_U_H_AUDIO_2, + PCI_DID_INTEL_PTL_U_H_AUDIO_3, + PCI_DID_INTEL_PTL_U_H_AUDIO_4, + PCI_DID_INTEL_PTL_U_H_AUDIO_5, + PCI_DID_INTEL_PTL_U_H_AUDIO_6, + PCI_DID_INTEL_PTL_U_H_AUDIO_7, + PCI_DID_INTEL_PTL_U_H_AUDIO_8, PCI_DID_INTEL_LNL_AUDIO_1, PCI_DID_INTEL_LNL_AUDIO_2, PCI_DID_INTEL_LNL_AUDIO_3, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index ca50312..59ecb50 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -21,14 +21,22 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_AUDIO_1, - PCI_DID_INTEL_PTL_AUDIO_2, - PCI_DID_INTEL_PTL_AUDIO_3, - PCI_DID_INTEL_PTL_AUDIO_4, - PCI_DID_INTEL_PTL_AUDIO_5, - PCI_DID_INTEL_PTL_AUDIO_6, - PCI_DID_INTEL_PTL_AUDIO_7, - PCI_DID_INTEL_PTL_AUDIO_8, + PCI_DID_INTEL_PTL_H_AUDIO_1, + PCI_DID_INTEL_PTL_H_AUDIO_2, + PCI_DID_INTEL_PTL_H_AUDIO_3, + PCI_DID_INTEL_PTL_H_AUDIO_4, + PCI_DID_INTEL_PTL_H_AUDIO_5, + PCI_DID_INTEL_PTL_H_AUDIO_6, + PCI_DID_INTEL_PTL_H_AUDIO_7, + PCI_DID_INTEL_PTL_H_AUDIO_8, + PCI_DID_INTEL_PTL_U_H_AUDIO_1, + PCI_DID_INTEL_PTL_U_H_AUDIO_2, + PCI_DID_INTEL_PTL_U_H_AUDIO_3, + PCI_DID_INTEL_PTL_U_H_AUDIO_4, + PCI_DID_INTEL_PTL_U_H_AUDIO_5, + PCI_DID_INTEL_PTL_U_H_AUDIO_6, + PCI_DID_INTEL_PTL_U_H_AUDIO_7, + PCI_DID_INTEL_PTL_U_H_AUDIO_8, PCI_DID_INTEL_LNL_AUDIO_1, PCI_DID_INTEL_LNL_AUDIO_2, PCI_DID_INTEL_LNL_AUDIO_3, -- To view, visit
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c9e420a6ae19d00fb5510c99d4c219dc43ad3c0 Gerrit-Change-Number: 83516 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[XS] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for SRAM
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83515?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for SRAM ...................................................................... device/pci_ids: Add new Intel PTL device IDs for SRAM This patch adds new SRAM PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SRAM driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ib6d62dad59965258dab453533dface9c359de586 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83515
Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/sram/sram.c 2 files changed, 4 insertions(+), 2 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6d3911f..dac7508 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4549,7 +4549,8 @@ #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf #define PCI_DID_INTEL_LNL_SRAM 0xa87f -#define PCI_DID_INTEL_PTL_SRAM 0xe47f +#define PCI_DID_INTEL_PTL_H_SRAM 0xe47f +#define PCI_DID_INTEL_PTL_U_H_SRAM 0xe37f /* Intel AUDIO device Ids */ #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 649a6c6..e63f805 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -33,7 +33,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_SRAM, + PCI_DID_INTEL_PTL_H_SRAM, + PCI_DID_INTEL_PTL_U_H_SRAM, PCI_DID_INTEL_LNL_SRAM, PCI_DID_INTEL_MTL_SOC_SRAM, PCI_DID_INTEL_MTL_IOE_M_SRAM, -- To view, visit
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6d62dad59965258dab453533dface9c359de586 Gerrit-Change-Number: 83515 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[S] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for P2SBx
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83514?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for P2SBx ...................................................................... device/pci_ids: Add new Intel PTL device IDs for P2SBx This patch adds new P2SBx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the P2SBx driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie1c36bc1c014bb1e219afe0cafb6c9941f253b0c Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83514
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c 3 files changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5fa478f..6d3911f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4530,8 +4530,10 @@ #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 #define PCI_DID_INTEL_LNL_P2SB2 0xa84c -#define PCI_DID_INTEL_PTL_P2SB 0xe420 -#define PCI_DID_INTEL_PTL_P2SB2 0xe44c +#define PCI_DID_INTEL_PTL_H_P2SB 0xe420 +#define PCI_DID_INTEL_PTL_H_P2SB2 0xe44c +#define PCI_DID_INTEL_PTL_U_H_P2SB 0xe320 +#define PCI_DID_INTEL_PTL_U_H_P2SB2 0xe34c /* Intel SRAM device Ids */ #define PCI_DID_INTEL_APL_SRAM 0x5aec diff --git a/src/soc/intel/common/block/p2sb/ioe_p2sb.c b/src/soc/intel/common/block/p2sb/ioe_p2sb.c index 769b853..3f45e69 100644 --- a/src/soc/intel/common/block/p2sb/ioe_p2sb.c +++ b/src/soc/intel/common/block/p2sb/ioe_p2sb.c @@ -37,6 +37,8 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_H_P2SB2, + PCI_DID_INTEL_PTL_U_H_P2SB2, PCI_DID_INTEL_MTL_IOE_M_P2SB, PCI_DID_INTEL_MTL_IOE_P_P2SB, 0, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index e348501..16f78da 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -137,6 +137,8 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DID_INTEL_PTL_H_P2SB, + PCI_DID_INTEL_PTL_U_H_P2SB, PCI_DID_INTEL_LNL_P2SB, PCI_DID_INTEL_MTL_SOC_P2SB, PCI_DID_INTEL_RPP_P_P2SB, -- To view, visit
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1c36bc1c014bb1e219afe0cafb6c9941f253b0c Gerrit-Change-Number: 83514 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[S] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for XHCI/TCSS XHCI
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83513?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for XHCI/TCSS XHCI ...................................................................... device/pci_ids: Add new Intel PTL device IDs for XHCI/TCSS XHCI This patch adds new XHCI/TCSS XHCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XHCI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5ae8f493374087a5e684e0a04486cd64cea6f335 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83513
Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xhci/xhci.c 3 files changed, 8 insertions(+), 4 deletions(-) Approvals: Eric Lai: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4674f7b..5fa478f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4498,8 +4498,10 @@ #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d #define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831 -#define PCI_DID_INTEL_PTL_XHCI 0xe47d -#define PCI_DID_INTEL_PTL_TCSS_XHCI 0xe431 +#define PCI_DID_INTEL_PTL_H_XHCI 0xe47d +#define PCI_DID_INTEL_PTL_H_TCSS_XHCI 0xe431 +#define PCI_DID_INTEL_PTL_U_H_XHCI 0xe37d +#define PCI_DID_INTEL_PTL_U_H_TCSS_XHCI 0xe331 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index 4e1a2a8..8776e4d 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -26,7 +26,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_TCSS_XHCI, + PCI_DID_INTEL_PTL_H_TCSS_XHCI, + PCI_DID_INTEL_PTL_U_H_TCSS_XHCI, PCI_DID_INTEL_LNL_TCSS_XHCI, PCI_DID_INTEL_RPP_P_TCSS_XHCI, PCI_DID_INTEL_MTL_M_TCSS_XHCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index dd4e5de..c1f300a 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -131,7 +131,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_XHCI, + PCI_DID_INTEL_PTL_H_XHCI, + PCI_DID_INTEL_PTL_U_H_XHCI, PCI_DID_INTEL_LNL_XHCI, PCI_DID_INTEL_MTL_XHCI, PCI_DID_INTEL_APL_XHCI, -- To view, visit
https://review.coreboot.org/c/coreboot/+/83513?usp=email
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ae8f493374087a5e684e0a04486cd64cea6f335 Gerrit-Change-Number: 83513 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[XS] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for SMBUS
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83512?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for SMBUS ...................................................................... device/pci_ids: Add new Intel PTL device IDs for SMBUS This patch adds new SMBUS PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SMBUS driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I4b8b59cf4e005f0e17a25d0fbe761404dab432b3 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83512
Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/smbus/smbus.c 2 files changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ce27e53..4674f7b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4454,7 +4454,8 @@ #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 -#define PCI_DID_INTEL_PTL_SMBUS 0xe422 +#define PCI_DID_INTEL_PTL_H_SMBUS 0xe422 +#define PCI_DID_INTEL_PTL_U_H_SMBUS 0xe322 /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 7f87a52..37e0cd2 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -49,7 +49,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_SMBUS, + PCI_DID_INTEL_PTL_H_SMBUS, + PCI_DID_INTEL_PTL_U_H_SMBUS, PCI_DID_INTEL_LNL_SMBUS, PCI_DID_INTEL_MTL_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS, -- To view, visit
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b8b59cf4e005f0e17a25d0fbe761404dab432b3 Gerrit-Change-Number: 83512 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[S] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIx
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83511?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIx ...................................................................... device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIx This patch adds new Fast-SPI and GSPIx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SPI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5c7c0be6f219c93d4520494857d31ce1cf939f36 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83511
Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/spi/spi.c 2 files changed, 16 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 69bfc92..ce27e53 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4102,10 +4102,14 @@ #define PCI_DID_INTEL_LNL_GSPI1 0xa830 #define PCI_DID_INTEL_LNL_GSPI2 0xa846 -#define PCI_DID_INTEL_PTL_HWSEQ_SPI 0xe423 -#define PCI_DID_INTEL_PTL_SPI0 0xe427 -#define PCI_DID_INTEL_PTL_SPI1 0xe430 -#define PCI_DID_INTEL_PTL_SPI2 0xe446 +#define PCI_DID_INTEL_PTL_H_HWSEQ_SPI 0xe423 +#define PCI_DID_INTEL_PTL_H_SPI0 0xe427 +#define PCI_DID_INTEL_PTL_H_SPI1 0xe430 +#define PCI_DID_INTEL_PTL_H_SPI2 0xe446 +#define PCI_DID_INTEL_PTL_U_H_HWSEQ_SPI 0xe323 +#define PCI_DID_INTEL_PTL_U_H_SPI0 0xe327 +#define PCI_DID_INTEL_PTL_U_H_SPI1 0xe330 +#define PCI_DID_INTEL_PTL_U_H_SPI2 0xe346 /* Intel IGD device Ids */ #define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902 diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 0e8aa26..74f9e31 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -123,10 +123,14 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_HWSEQ_SPI, - PCI_DID_INTEL_PTL_SPI0, - PCI_DID_INTEL_PTL_SPI1, - PCI_DID_INTEL_PTL_SPI2, + PCI_DID_INTEL_PTL_H_HWSEQ_SPI, + PCI_DID_INTEL_PTL_H_SPI0, + PCI_DID_INTEL_PTL_H_SPI1, + PCI_DID_INTEL_PTL_H_SPI2, + PCI_DID_INTEL_PTL_U_H_HWSEQ_SPI, + PCI_DID_INTEL_PTL_U_H_SPI0, + PCI_DID_INTEL_PTL_U_H_SPI1, + PCI_DID_INTEL_PTL_U_H_SPI2, PCI_DID_INTEL_LNL_GSPI0, PCI_DID_INTEL_LNL_GSPI1, PCI_DID_INTEL_LNL_GSPI2, -- To view, visit
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c7c0be6f219c93d4520494857d31ce1cf939f36 Gerrit-Change-Number: 83511 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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[S] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for UARTx
by Subrata Banik (Code Review)
19 Jul '24
19 Jul '24
Subrata Banik has submitted this change. (
https://review.coreboot.org/c/coreboot/+/83510?usp=email
) Change subject: device/pci_ids: Add new Intel PTL device IDs for UARTx ...................................................................... device/pci_ids: Add new Intel PTL device IDs for UARTx This patch adds new UARTx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the UART driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I384a753f08ae5a752cef6009d07104e8ff4b4a6e Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on:
https://review.coreboot.org/c/coreboot/+/83510
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/uart/uart.c 2 files changed, 18 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 967f657..69bfc92 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3996,9 +3996,12 @@ #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 -#define PCI_DID_INTEL_PTL_UART0 0xe425 -#define PCI_DID_INTEL_PTL_UART1 0xe426 -#define PCI_DID_INTEL_PTL_UART2 0xe452 +#define PCI_DID_INTEL_PTL_H_UART0 0xe425 +#define PCI_DID_INTEL_PTL_H_UART1 0xe426 +#define PCI_DID_INTEL_PTL_H_UART2 0xe452 +#define PCI_DID_INTEL_PTL_U_H_UART0 0xe325 +#define PCI_DID_INTEL_PTL_U_H_UART1 0xe326 +#define PCI_DID_INTEL_PTL_U_H_UART2 0xe352 /* Intel SPI device Ids */ #define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65 diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index e454f7e..ef83f53 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -308,7 +308,8 @@ static const char *uart_acpi_name(const struct device *dev) { switch (dev->device) { - case PCI_DID_INTEL_PTL_UART0: + case PCI_DID_INTEL_PTL_H_UART0: + case PCI_DID_INTEL_PTL_U_H_UART0: case PCI_DID_INTEL_LNL_UART0: case PCI_DID_INTEL_ADP_P_UART0: case PCI_DID_INTEL_APL_UART0: @@ -317,7 +318,8 @@ case PCI_DID_INTEL_SPT_H_UART0: case PCI_DID_INTEL_CNP_H_UART0: return "UAR0"; - case PCI_DID_INTEL_PTL_UART1: + case PCI_DID_INTEL_PTL_H_UART1: + case PCI_DID_INTEL_PTL_U_H_UART1: case PCI_DID_INTEL_LNL_UART1: case PCI_DID_INTEL_ADP_P_UART1: case PCI_DID_INTEL_APL_UART1: @@ -326,7 +328,8 @@ case PCI_DID_INTEL_SPT_H_UART1: case PCI_DID_INTEL_CNP_H_UART1: return "UAR1"; - case PCI_DID_INTEL_PTL_UART2: + case PCI_DID_INTEL_PTL_H_UART2: + case PCI_DID_INTEL_PTL_U_H_UART2: case PCI_DID_INTEL_LNL_UART2: case PCI_DID_INTEL_ADP_P_UART2: case PCI_DID_INTEL_APL_UART2: @@ -354,9 +357,12 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DID_INTEL_PTL_UART0, - PCI_DID_INTEL_PTL_UART1, - PCI_DID_INTEL_PTL_UART2, + PCI_DID_INTEL_PTL_H_UART0, + PCI_DID_INTEL_PTL_H_UART1, + PCI_DID_INTEL_PTL_H_UART2, + PCI_DID_INTEL_PTL_U_H_UART0, + PCI_DID_INTEL_PTL_U_H_UART1, + PCI_DID_INTEL_PTL_U_H_UART2, PCI_DID_INTEL_LNL_UART0, PCI_DID_INTEL_LNL_UART1, PCI_DID_INTEL_LNL_UART2, -- To view, visit
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Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I384a753f08ae5a752cef6009d07104e8ff4b4a6e Gerrit-Change-Number: 83510 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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