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Change subject: Makefile.mk: Remove linker warning on RWX segments
......................................................................
Makefile.mk: Remove linker warning on RWX segments
Silence a linker warnings about segments with RWX. Having one segment
for all sections is a good design choice as it makes parsing the elf
into a loadable binary simpler.
Change-Id: I1e0f51c69dabaea314ac45924474d446a9ab68f4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/83559/3
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Gerrit-Change-Number: 83559
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Change subject: Makefile.mk: Mark stack as not executable
......................................................................
Makefile.mk: Mark stack as not executable
Suppress the warning:
missing .note.GNU-stack section implies executable stack
NOTE: This behaviour is deprecated and will be removed in a
future version of the linker
Since we don't need an executable stack this is fine. Some newer
linkers like LLD even default to this.
Change-Id: Ib787cc464e0924ab57575cec9fbfd1d59bdd3481
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/83560/3
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Hello Jérémy Compostella,
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Change subject: arch/x86/Makefile.mk: Remove obsolete romcc reference
......................................................................
arch/x86/Makefile.mk: Remove obsolete romcc reference
No assembly.inc file is being generated by romcc anymore.
Change-Id: I57a3a6e1c2cf7cf30fb0cd94cc8455f715050490
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Makefile.mk
M src/northbridge/intel/sandybridge/mrc_wrapper.S
2 files changed, 1 insertion(+), 4 deletions(-)
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Change subject: soc/mediatek: Move memmory macros into MTK common directory
......................................................................
soc/mediatek: Move memmory macros into MTK common directory
Because the memory macros of MTK SOCs are gernerally the same.
Share a common memlayout.h.
TEST=rauru build pass.
BUG=b:317009620
Change-Id: Iea4add8fe3735085c13438a2e177bec177913191
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
A src/soc/mediatek/common/include/soc/memlayout.h
M src/soc/mediatek/mt8173/memlayout.ld
M src/soc/mediatek/mt8183/memlayout.ld
M src/soc/mediatek/mt8186/include/soc/memlayout.ld
M src/soc/mediatek/mt8188/include/soc/memlayout.ld
M src/soc/mediatek/mt8195/include/soc/memlayout.ld
6 files changed, 28 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83571/1
diff --git a/src/soc/mediatek/common/include/soc/memlayout.h b/src/soc/mediatek/common/include/soc/memlayout.h
new file mode 100644
index 0000000..f51c2a1
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/memlayout.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+/*
+ * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
+ * It will be returned before starting the ramstage.
+ * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
+ */
+#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
+#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
+#define DRAM_INIT_CODE(addr, size) \
+ REGION(dram_init_code, addr, size, 64K)
+
+#define DRAM_DMA(addr, size) \
+ REGION(dram_dma, addr, size, 4K) \
+ _ = ASSERT(size % 4K == 0, \
+ "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
+#define EARLY_INIT(addr, size) \
+ REGION(early_init_data, addr, size, 4)
diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld
index 224dbda..c593853 100644
--- a/src/soc/mediatek/mt8173/memlayout.ld
+++ b/src/soc/mediatek/mt8173/memlayout.ld
@@ -1,21 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
SECTIONS
{
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index c5d9d08..b1b9027 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -1,23 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 4)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
SECTIONS
{
diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
index f927b60..a47e7c5 100644
--- a/src/soc/mediatek/mt8186/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
@@ -1,23 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 64K)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
SECTIONS
{
diff --git a/src/soc/mediatek/mt8188/include/soc/memlayout.ld b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
index ed3b71b..3dc386e 100644
--- a/src/soc/mediatek/mt8188/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8188/include/soc/memlayout.ld
@@ -1,19 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-#include <memlayout.h>
-#include <arch/header.ld>
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 64K)
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
+
SECTIONS
{
/* MT8188 has 192KB SRAM in total. */
diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
index 06806c5..ec8fa9c 100644
--- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld
@@ -1,26 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 64K)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
-
-#define EARLY_INIT(addr, size) \
- REGION(early_init_data, addr, size, 4)
+#include <soc/memlayout.h>
SECTIONS
{
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Rishika Raj has posted comments on this change by Rishika Raj. ( https://review.coreboot.org/c/coreboot/+/83540?usp=email )
Change subject: soc/intel/meteorlake: Increase CAR STACK_SIZE by 31KB to meet coreboot requirements
......................................................................
Patch Set 5:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83540/comment/f4d01d0e_9740b325?us… :
PS1, Line 2: rishikraj
> Please use Rishika Raj: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83540/comment/c3ed380c_fce3fbe2?us… :
PS1, Line 7: soc/intel/meteorlake: Change DCACHE_BSP_STACK_SIZE
> Maybe even: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83540/comment/7b4fa1f4_1c10050d?us… :
PS1, Line 8:
> > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83540/comment/aa005029_8d9638cf?us… :
PS1, Line 9: as required by the coreboot
> Please elaborate.
Acknowledged
https://review.coreboot.org/c/coreboot/+/83540/comment/ec206abc_d6012b7a?us… :
PS1, Line 9: 1KB to 512KB + 32KB
> Use just one space where there are two?
Acknowledged
https://review.coreboot.org/c/coreboot/+/83540/comment/e5ca5ac0_a2f3974a?us… :
PS1, Line 11: Bug
> BUG
Acknowledged
https://review.coreboot.org/c/coreboot/+/83540/comment/632e6e1c_bf44561c?us… :
PS1, Line 12: Test
> TEST
Acknowledged
Commit Message:
https://review.coreboot.org/c/coreboot/+/83540/comment/38bf871a_c9f649d8?us… :
PS2, Line 7: Incrase
> typo?
Acknowledged
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