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Change subject: soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
......................................................................
soc/intel/xeon_sp: Share save_dimm_info among Xeon-SP SoCs
TEST=Build and boot on archercity CRB
No changes in boot log and 'dmidecode' result under centos
TEST=Build and boot on avenuecity CRB
It will add DMI type 16,17,19,20
Change-Id: I2f5b7a4ffabed033d54d4724b3c41246503166fe
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/cpx/romstage.c
M src/soc/intel/xeon_sp/gnr/romstage.c
M src/soc/intel/xeon_sp/include/soc/romstage.h
M src/soc/intel/xeon_sp/romstage.c
M src/soc/intel/xeon_sp/spr/romstage.c
5 files changed, 156 insertions(+), 172 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83325/4
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Change subject: soc/amd: Ensure bank 0 is selected before accessing VBNV in CMOS
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/common/vboot/vbnv_cmos.c:
https://review.coreboot.org/c/coreboot/+/83495/comment/ac77c8f3_2512961b?us… :
PS4, Line 16: cmos_write(RTC_FREQ_SELECT_AMD, RTC_FREQ_SELECT);
> > Also the issue is happening only in MonkeyIsland and not on Zork(prior generation) or Skyrim(later […]
```
#define PSP_SRAM_START 0x26000
#define PSP_SRAM_SIZE (148K)
#define PSP_VERSTAGE_STACK_START 0x41000
#define PSP_VERSTAGE_STACK_SIZE (40K)
```
The stack takes 40K, leaving only 108K for verstage plus memlayout_transfer_buffer.inc. Reducing the stack size by 4K in CB:83564 seems to work.
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Change subject: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83537/comment/7649069e_46bb9f2c?us… :
PS1, Line 17: [1] lore.kernel.org/lkml/20220523165815.913462426@linuxfoundation.org
> I’d add the scheme https://, and also use git.kernel.org and not the list.
Done
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Change subject: drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
......................................................................
drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.
To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/d…
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/drivers/pc80/rtc/mc146818rtc.c
M src/include/pc80/mc146818rtc.h
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/83537/3
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Change subject: soc/intel/xeon_sp/spr: Return updated resource index for create_ioat_domain
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/83195/comment/e47b33ba_4d825ecd?us… :
PS6, Line 63: unsigned int index = 0;
> This should be initialised to the value of `res_count` if valid, and only fall back to 0 if it's NUL […]
Done
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Change subject: soc/intel/xeon_sp/spr: Return updated resource index for create_ioat_domain
......................................................................
soc/intel/xeon_sp/spr: Return updated resource index for create_ioat_domain
create_ioat_domain creates the domain device with a number of
resources. Return the updated resource index so that the updated
index could be used as the starting index for additional resource
creation outside create_ioat_domain.
TEST=Build and boot on intel/archercity CRB
Change-Id: I9e719ae8407c7f31f88dbb407f003e2ded8f0faf
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/spr/ioat.c
1 file changed, 13 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/83195/7
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Change subject: Makefile.mk: Reorganize CFLAGS_common
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83452/comment/46686881_01438744?us… :
PS4, Line 507: # Options controlling the kind of output
> I'll remove those comments, but in that case, the sorting will not be easy to understand. […]
Done
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Change subject: Makefile.mk: Reorganize CFLAGS_common
......................................................................
Patch Set 6:
(1 comment)
File Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83452/comment/89922b11_8b2be984?us… :
PS4, Line 543: CFLAGS_common += -g
> In general, it is best to place the -g option at the end of the compilation flags list.
Why? I mean, there are more added below. So this is not the end.
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Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83494?usp=email )
Change subject: security/vboot: Introduce vbnv_platform_init_cmos()
......................................................................
security/vboot: Introduce vbnv_platform_init_cmos()
Most x86 platforms use CMOS as the vboot nvdata (VBNV) backend storage.
On some platforms such as AMD, certain CMOS registers must be configured
before accessing the CMOS RAM which contains VBNV. More precisely,
according to AMD's spec [1], the bit 4 of Register A of CMOS is bank
selection. Since VBNV is accessed via bank 0 (see the MC146818 driver),
the bit must be cleared before the VBNV can be successfully written to
CMOS. Saving VBNV to CMOS may fail in verstage, if CMOS has lost power.
In that case, all the CMOS registers would contain garbage data.
Therefore, for AMD platforms the bit must be cleared in verstage, prior
to the first save_vbnv_cmos() call.
Introduce vbnv_platform_init_cmos(), which is no-op by default, and can
be defined per platform. The function will be called from vbnv_init() if
VBOOT_VBNV_CMOS.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: Ic899a827bd6bb8ab1473f8c6c03b9fde96ea6823
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83494
Reviewed-by: Bao Zheng <fishbaozi(a)gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/security/vboot/vbnv.h
M src/security/vboot/vbnv_cmos.c
2 files changed, 8 insertions(+), 0 deletions(-)
Approvals:
Karthik Ramasubramanian: Looks good to me, approved
build bot (Jenkins): Verified
Bao Zheng: Looks good to me, but someone else must approve
diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h
index c4112a2..49d1f12 100644
--- a/src/security/vboot/vbnv.h
+++ b/src/security/vboot/vbnv.h
@@ -23,6 +23,8 @@
/* Initialize the vbnv CMOS backing store. The vbnv_copy pointer is used for
optional temporary storage in the init function. */
void vbnv_init_cmos(uint8_t *vbnv_copy);
+/* Platform-specific CMOS init function, called by vbnv_init_cmos(). */
+void vbnv_platform_init_cmos(void);
/* Return non-zero if CMOS power was lost. */
int vbnv_cmos_failed(void);
void read_vbnv_cmos(uint8_t *vbnv_copy);
diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c
index 35e4c41..5073509 100644
--- a/src/security/vboot/vbnv_cmos.c
+++ b/src/security/vboot/vbnv_cmos.c
@@ -67,8 +67,14 @@
cmos_write(vbnv_copy[i], CONFIG_VBOOT_VBNV_OFFSET + 14 + i);
}
+void __weak vbnv_platform_init_cmos(void)
+{
+}
+
void vbnv_init_cmos(uint8_t *vbnv_copy)
{
+ vbnv_platform_init_cmos();
+
/* If no CMOS failure just defer to the normal read path for checking
vbnv contents' integrity. */
if (!vbnv_cmos_failed())
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Gerrit-PatchSet: 4
Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>