coreboot-gerrit May 2024

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[S] Change in coreboot[main]: mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports
by Pranava Y N (Code Review) 28 May '24

28 May '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pranava Y N. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82637?usp=email to look at the new patch set (#4). Change subject: mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports ...................................................................... mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports The devicetree entry and gpio.c updated as per the schematics of Trulo to map the OC fault signals from A0/A1 USB ports. BUG=b:335858378 TEST= Able to build google/trulo Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/trulo/gpio.c M src/mainboard/google/brya/variants/trulo/overridetree.cb 2 files changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/82637/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Gerrit-Change-Number: 82637 Gerrit-PatchSet: 4 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in libgfxinit[cros]: gma: Add graphics id for tivviks
by Dinesh Gehlot (Code Review) 28 May '24

28 May '24

Attention is currently required from: Angel Pons, Angel Pons, Subrata Banik. Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/libgfxinit/+/82681?usp=email ) Change subject: gma: Add graphics id for tivviks ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/libgfxinit/+/82681/comment/08bb6c78_33370e7c?… : PS1, Line 9: graphics > TWL graphics id Acknowledged -- To view, visit https://review.coreboot.org/c/libgfxinit/+/82681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: libgfxinit Gerrit-Branch: cros Gerrit-Change-Id: I23a19ab99e1bd1bc88f472116097f364b48d5b79 Gerrit-Change-Number: 82681 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Tue, 28 May 2024 09:56:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in libgfxinit[cros]: gma: Add graphics id for tivviks
by Dinesh Gehlot (Code Review) 28 May '24

28 May '24

Attention is currently required from: Angel Pons, Angel Pons, Dinesh Gehlot. Hello Angel Pons, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/82681?usp=email to look at the new patch set (#2). Change subject: gma: Add graphics id for tivviks ...................................................................... gma: Add graphics id for tivviks This patch includes the TWL graphics id for the Tivviks board. BUG=b:343004931 TEST=eSOL verified on tivviks board. Change-Id: I23a19ab99e1bd1bc88f472116097f364b48d5b79 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M common/hw-gfx-gma-config.ads.template 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/81/82681/2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/82681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: libgfxinit Gerrit-Branch: cros Gerrit-Change-Id: I23a19ab99e1bd1bc88f472116097f364b48d5b79 Gerrit-Change-Number: 82681 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Add WWAN power off sequence
by Leo Chou (Code Review) 28 May '24

28 May '24

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82683?usp=email ) Change subject: mb/google/nissa/var/sundance: Add WWAN power off sequence ...................................................................... mb/google/nissa/var/sundance: Add WWAN power off sequence Sundance support FM101 WWAN, use wwan_power.asl to handle the power off sequence BUG=b:343139385 TEST=Build and boot on sundance Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/sundance/include/variant/gpio.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/82683/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index fcc2e63..366d2dd 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -413,6 +413,7 @@ config BOARD_GOOGLE_SUNDANCE select BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_GENERIC_GPIO_KEYS + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_PUJJOGA select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/82683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Gerrit-Change-Number: 82683 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
by Lean Sheng Tan (Code Review) 28 May '24

28 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81443?usp=email ) Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ...................................................................... soc/intel/xeon_sp: Add PD_TYPE_CLUSTER Add a new proximity type to represent the sub-NUMA cluster (SNC). This patch adds necessary Xeon-SP common code level support for SNC support. When SNC on, each SNC cluster will have a proximity domain. DIMMs and CPU cores are attached to SNC proximity domains instead of the processor proximity domains. With SNC, there are 3 types of proximity domains, PD_TYPE_PROCESSOR, PD_TYPE_GENERIC_INITIATOR and PD_TYPE_CLUSTER. proximity domain type checks in Xeon-SP codes are updated to correctly handle the adding of the new type. This patch doesn't actually enable SNC. To fully enable SNC, SoC codes need to override soc_get_cluster_count(), soc_set_cpu_node_ id() and memory_to_pd(), and call soc_set_cpu_node_id() in its per-CPU init routine. Change-Id: I32558983780f302ff4893901540a90baebf47add Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Co-authored-by: Ziang Wang <ziang.wang(a)intel.com> Co-authored-by: Gang Chen <gang.c.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81443 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 5 files changed, 81 insertions(+), 12 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h index d124517..b644881 100644 --- a/src/soc/intel/xeon_sp/include/soc/numa.h +++ b/src/soc/intel/xeon_sp/include/soc/numa.h @@ -19,6 +19,17 @@ * Generic Initiator domain is a CXL memory device. */ PD_TYPE_GENERIC_INITIATOR, + /* + * PD_TYPE_CLUSTER is for Sub-NUMA cluster (SNC). SNC is localization + * domain within a socket, composed of a set of CPU cores, last-level + * cache pieces and memory controllers, which are close to each other. + * SNC will be reported as NUMA nodes to OS so that the performance + * proximity could be fully exploited for task assignment and scheduling. + * + * For more, please refer to + * https://www.intel.com/content/www/us/en/developer/articles/technical/xeon-p… + */ + PD_TYPE_CLUSTER, PD_TYPE_MAX }; @@ -40,6 +51,7 @@ * sockets, so we need a bitmap. */ uint8_t socket_bitmap; + uint8_t cluster_bitmap; /* Relative distances (memory latency) from all domains */ uint8_t *distances; /* @@ -68,4 +80,7 @@ uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem); uint32_t device_to_pd(const struct device *dev); +uint8_t soc_get_cluster_count(void); +void soc_set_cpu_node_id(struct device *cpu); + #endif /* NUMA_H */ diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 1f0b9a3..8ce4981 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -25,6 +25,9 @@ printk(BIOS_DEBUG, "\t\tbase(64MB):0x%x\n", pds.pds[i].base); printk(BIOS_DEBUG, "\t\tsize(64MB):0x%x\n", pds.pds[i].size); } + if (pds.pds[i].pd_type == PD_TYPE_CLUSTER) { + printk(BIOS_DEBUG, "\t\tcluster_bitmap:0x%x\n", pds.pds[i].cluster_bitmap); + } } } @@ -32,20 +35,25 @@ { uint8_t num_sockets = soc_get_num_cpus(); uint8_t num_cxlnodes = get_cxl_node_count(); + uint8_t num_clusters = soc_get_cluster_count(); const IIO_UDS *hob = get_iio_uds(); /* * Rules/assumptions: - * 1. Each processor has a processor proximity domain regardless whether + * 1. Each socket has a processor proximity domain regardless whether * a processor has DIMM attached to it or not. - * 2. All system memory map elements are either from processor attached memory, + * 2. When sub-NUMA cluster (SNC) is on, soc_get_cluster_count() will return a + * non-zero value and each SNC cluster will have one proximity domain. + * For SNC case, DIMMs and CPU cores are attached to SNC proximity domains instead + * of the processor proximity domains. + * 3. All system memory map elements are either from processor attached memory, * or from CXL memory. Each CXL node info entry has a corresponding entry * in system memory map elements. - * 3. Each CXL device may have multiple HDMs (Host-managed Device Memory). Each + * 4. Each CXL device may have multiple HDMs (Host-managed Device Memory). Each * HDM has one and only one CXL node info entry. Each CXL node info entry * represents a generic initiator proximity domain. */ - pds.num_pds = num_cxlnodes + num_sockets; + pds.num_pds = num_cxlnodes + num_sockets + num_sockets * num_clusters; pds.pds = xmalloc(sizeof(struct proximity_domain) * pds.num_pds); if (!pds.pds) die("%s %d out of memory.", __FILE__, __LINE__); @@ -57,12 +65,23 @@ for (uint8_t socket = 0; socket < num_sockets; socket++) { if (!soc_cpu_is_enabled(socket)) continue; + const uint8_t socket_id = hob->PlatformData.IIO_resource[socket].SocketID; pds.pds[i].pd_type = PD_TYPE_PROCESSOR; - pds.pds[i].socket_bitmap = 1 << hob->PlatformData.IIO_resource[socket].SocketID; + pds.pds[i].socket_bitmap = 1 << socket_id; pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); i++; + /* Fill in cluster domains */ + for (uint8_t cluster = 0; cluster < num_clusters; cluster++) { + pds.pds[i].pd_type = PD_TYPE_CLUSTER; + pds.pds[i].socket_bitmap = 1 << socket_id; + pds.pds[i].cluster_bitmap = 1 << cluster; + pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); + if (!pds.pds[i].distances) + die("%s %d out of memory.", __FILE__, __LINE__); + i++; + } } /* If there are no CXL nodes, we are done */ @@ -100,7 +119,7 @@ uint32_t size = 0; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; size += pds.pds[i].size; } @@ -123,6 +142,22 @@ return XEONSP_INVALID_PD_INDEX; } +static uint32_t cluster_to_pd(uint8_t socket, uint8_t cluster) +{ + for (uint8_t i = 0; i < pds.num_pds; i++) { + if (pds.pds[i].pd_type != PD_TYPE_CLUSTER) + continue; + if (pds.pds[i].socket_bitmap == (1 << socket) && + pds.pds[i].cluster_bitmap == (1 << cluster)) + return i; + } + + printk(BIOS_ERR, "%s: could not find proximity domain for socket/cluster %d/%d.\n", + __func__, socket, cluster); + + return XEONSP_INVALID_PD_INDEX; +} + uint32_t device_to_pd(const struct device *dev) { /* first to see if the dev is bound to specific pd */ @@ -130,8 +165,12 @@ if (pds.pds[i].dev == dev) return i; - if (dev->path.type == DEVICE_PATH_APIC) - return socket_to_pd(dev->path.apic.package_id); + if (dev->path.type == DEVICE_PATH_APIC) { + if (soc_get_cluster_count()) + return cluster_to_pd(dev->path.apic.package_id, dev->path.apic.node_id); + else + return socket_to_pd(dev->path.apic.package_id); + } if ((dev->path.type == DEVICE_PATH_DOMAIN) || (dev->path.type == DEVICE_PATH_PCI)) @@ -143,8 +182,12 @@ return XEONSP_INVALID_PD_INDEX; } -uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem) +__weak uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem) { + /* + * TODO: For SNC case, link DRAM range to cluster id instead of socket id + * in SoC codes. + */ return socket_to_pd(mem->SocketId); } @@ -183,3 +226,14 @@ fill_pd_distances(); dump_pds(); } + +__weak uint8_t soc_get_cluster_count(void) +{ + //TODO: Implement in SoC codes. + return 0; +} + +__weak void soc_set_cpu_node_id(struct device *cpu) +{ + //TODO: Implement in SoC codes. +}; diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 1eab917..e179df0 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -176,7 +176,7 @@ uint32_t ep_bus; uint8_t i; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; ep_bus = PCI_BDF(pds.pds[i].dev) >> 20; if (ep_bus == ecrc_bus + 1) diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 17addfc..5845327 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -94,7 +94,7 @@ assert(pds.num_pds); for (uint8_t i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; uint32_t bus = PCI_BDF(pds.pds[i].dev) >> 20; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a6ac7c8..d2d4622 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -284,7 +284,7 @@ /* CXL Memory */ uint8_t i; for (i = 0; i < pds.num_pds; i++) { - if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) continue; unsigned long flags = IORESOURCE_CACHEABLE; -- To view, visit https://review.coreboot.org/c/coreboot/+/81443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32558983780f302ff4893901540a90baebf47add Gerrit-Change-Number: 81443 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: include/device: Fix IO resource handling covering 0xFFFF
by Lean Sheng Tan (Code Review) 28 May '24

28 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82192?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: include/device: Fix IO resource handling covering 0xFFFF ...................................................................... include/device: Fix IO resource handling covering 0xFFFF IO resource creation utils taking 'from' and 'to' as parameters use uint16_t for them, where 'to' equals the resource limit plus 1. When a resource is with a limit of 0xFFFF, the value of 'to' will be clipped to 0x0000 by uint16_t. Fix this problem by use uint32_t and checks the effective range to make sure it no larger than UINT16_MAX + 1. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: Ie83045683094d6330c1676809f83acf30175cc90 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82192 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/device/device.h 1 file changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/include/device/device.h b/src/include/device/device.h index 367635a..1b2e097 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -369,10 +369,12 @@ static inline const struct resource *fixed_io_from_to_flags(struct device *dev, unsigned long index, - uint16_t base, uint16_t end, unsigned long flags) + uint16_t base, uint32_t end, unsigned long flags) { if (end <= base) return NULL; + if (end > UINT16_MAX + 1) + return NULL; return fixed_io_range_flags(dev, index, base, end - base, flags); } @@ -393,10 +395,12 @@ static inline const struct resource *domain_io_window_from_to(struct device *dev, unsigned long index, - uint16_t base, uint16_t end) + uint16_t base, uint32_t end) { if (end <= base) return NULL; + if (end > UINT16_MAX + 1) + return NULL; return domain_io_window_range(dev, index, base, end - base); } -- To view, visit https://review.coreboot.org/c/coreboot/+/82192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie83045683094d6330c1676809f83acf30175cc90 Gerrit-Change-Number: 82192 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: include/device: Fix IO resource handling covering 0xFFFF
by Lean Sheng Tan (Code Review) 28 May '24

28 May '24

Attention is currently required from: Nico Huber, Patrick Rudolph, Shuo Liu. Lean Sheng Tan has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82192?usp=email ) Change subject: include/device: Fix IO resource handling covering 0xFFFF ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie83045683094d6330c1676809f83acf30175cc90 Gerrit-Change-Number: 82192 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Tue, 28 May 2024 09:45:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: include/device: Fix IO resource handling covering 0xFFFF
by Lean Sheng Tan (Code Review) 28 May '24

28 May '24

Attention is currently required from: Nico Huber, Patrick Rudolph, Shuo Liu. Lean Sheng Tan has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82192?usp=email ) Change subject: include/device: Fix IO resource handling covering 0xFFFF ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82192?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie83045683094d6330c1676809f83acf30175cc90 Gerrit-Change-Number: 82192 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Tue, 28 May 2024 09:45:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add domain resource window creation utils
by Lean Sheng Tan (Code Review) 28 May '24

28 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82103?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Add domain resource window creation utils ...................................................................... soc/intel/xeon_sp: Add domain resource window creation utils It might be benefical to have utils for domain resource window creation so that the correct IORESOURCE flags used could be guaranteed. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/soc/intel/xeon_sp/spr/ioat.c 5 files changed, 81 insertions(+), 85 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/device/device_util.c b/src/device/device_util.c index d91df76..5d62020 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -776,7 +776,7 @@ } } -const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index, +const struct resource *resource_range_idx(struct device *dev, unsigned long index, uint64_t base, uint64_t size, unsigned long flags) { struct resource *resource; @@ -785,8 +785,13 @@ resource = new_resource(dev, index); resource->base = base; - resource->size = size; - resource->flags = IORESOURCE_FIXED | IORESOURCE_ASSIGNED; + + if (flags & IORESOURCE_FIXED) + resource->size = size; + if (flags & IORESOURCE_BRIDGE) + resource->limit = base + size - 1; + + resource->flags = IORESOURCE_ASSIGNED; resource->flags |= flags; printk(BIOS_SPEW, "dev: %s, index: 0x%lx, base: 0x%llx, size: 0x%llx\n", diff --git a/src/include/device/device.h b/src/include/device/device.h index 48e539f..367635a 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -263,7 +263,7 @@ /* These are temporary resource constructors to get us through the migration away from open-coding all the IORESOURCE_FLAGS. */ -const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index, +const struct resource *resource_range_idx(struct device *dev, unsigned long index, uint64_t base, uint64_t size, unsigned long flags); @@ -272,7 +272,8 @@ uint64_t base, uint64_t size, unsigned long flags) { - return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_MEM | flags); + return resource_range_idx(dev, index, base, size, + IORESOURCE_FIXED | IORESOURCE_MEM | flags); } static inline @@ -285,6 +286,24 @@ } static inline +const struct resource *domain_mem_window_range(struct device *dev, unsigned long index, + uint64_t base, uint64_t size) +{ + return resource_range_idx(dev, index, base, size, + IORESOURCE_MEM | IORESOURCE_BRIDGE); +} + +static inline +const struct resource *domain_mem_window_from_to(struct device *dev, unsigned long index, + uint64_t base, uint64_t end) +{ + if (end <= base) + return NULL; + return domain_mem_window_range(dev, index, base, end - base); +} + + +static inline const struct resource *ram_range(struct device *dev, unsigned long index, uint64_t base, uint64_t size) { @@ -344,7 +363,8 @@ const struct resource *fixed_io_range_flags(struct device *dev, unsigned long index, uint16_t base, uint16_t size, unsigned long flags) { - return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_IO | flags); + return resource_range_idx(dev, index, base, size, + IORESOURCE_FIXED | IORESOURCE_IO | flags); } static inline @@ -363,6 +383,23 @@ return fixed_io_range_flags(dev, index, base, size, IORESOURCE_RESERVE); } +static inline +const struct resource *domain_io_window_range(struct device *dev, unsigned long index, + uint16_t base, uint16_t size) +{ + return resource_range_idx(dev, index, base, size, + IORESOURCE_IO | IORESOURCE_BRIDGE); +} + +static inline +const struct resource *domain_io_window_from_to(struct device *dev, unsigned long index, + uint16_t base, uint16_t end) +{ + if (end <= base) + return NULL; + return domain_io_window_range(dev, index, base, end - base); +} + /* Compatibility code */ static inline void fixed_mem_resource_kb(struct device *dev, unsigned long index, diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index b17b773..117de9c 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -27,7 +27,6 @@ static void iio_pci_domain_read_resources(struct device *dev) { - struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); if (!sr) @@ -37,36 +36,24 @@ if (is_domain0(dev)) { /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ - res = new_resource(dev, index++); + struct resource *res = new_resource(dev, index++); res->base = 0; res->size = 0x1000; res->limit = 0xfff; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } - if (sr->PciResourceIoBase < sr->PciResourceIoLimit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceIoBase; - res->limit = sr->PciResourceIoLimit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceIoBase < sr->PciResourceIoLimit) + domain_io_window_from_to(dev, index++, + sr->PciResourceIoBase, sr->PciResourceIoLimit + 1); - if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem32Base; - res->limit = sr->PciResourceMem32Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) + domain_mem_window_from_to(dev, index++, + sr->PciResourceMem32Base, sr->PciResourceMem32Limit + 1); - if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) { - res = new_resource(dev, index++); - res->base = sr->PciResourceMem64Base; - res->limit = sr->PciResourceMem64Limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) + domain_mem_window_from_to(dev, index++, + sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1); } /* @@ -129,7 +116,6 @@ #if CONFIG(SOC_INTEL_HAS_CXL) static void iio_cxl_domain_read_resources(struct device *dev) { - struct resource *res; const STACK_RES *sr = domain_to_stack_res(dev); if (!sr) @@ -137,29 +123,17 @@ int index = 0; - if (sr->IoBase < sr->PciResourceIoBase) { - res = new_resource(dev, index++); - res->base = sr->IoBase; - res->limit = sr->PciResourceIoBase - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (sr->IoBase < sr->PciResourceIoBase) + domain_io_window_from_to(dev, index++, + sr->IoBase, sr->PciResourceIoBase); - if (sr->Mmio32Base < sr->PciResourceMem32Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio32Base; - res->limit = sr->PciResourceMem32Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->Mmio32Base < sr->PciResourceMem32Base) + domain_mem_window_from_to(dev, index++, + sr->Mmio32Base, sr->PciResourceMem32Base); - if (sr->Mmio64Base < sr->PciResourceMem64Base) { - res = new_resource(dev, index++); - res->base = sr->Mmio64Base; - res->limit = sr->PciResourceMem64Base - 1; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (sr->Mmio64Base < sr->PciResourceMem64Base) + domain_mem_window_from_to(dev, index++, + sr->Mmio64Base, sr->PciResourceMem64Base); } static struct device_operations iio_cxl_domain_ops = { diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index a1b1b65..c4462d5 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -35,20 +35,16 @@ static void iio_pci_domain_read_resources(struct device *dev) { int index = 0; - struct resource *res; const UDS_PCIROOT_RES *pr = domain_to_pciroot_res(dev); /* Initialize the system-wide I/O space constraints. */ - if (pr->IoBase <= pr->IoLimit) { - res = new_resource(dev, index++); - res->base = pr->IoBase; - res->limit = pr->IoLimit; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; - } + if (pr->IoBase <= pr->IoLimit) + domain_io_window_from_to(dev, index++, + pr->IoBase, pr->IoLimit + 1); /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ if (is_domain0(dev)) { - res = new_resource(dev, index++); + struct resource *res = new_resource(dev, index++); res->base = 0; res->limit = 0xfff; res->size = 0x1000; @@ -56,20 +52,14 @@ } /* Initialize the system-wide memory resources constraints. */ - if (pr->Mmio32Base <= pr->Mmio32Limit) { - res = new_resource(dev, index++); - res->base = pr->Mmio32Base; - res->limit = pr->Mmio32Limit; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (pr->Mmio32Base <= pr->Mmio32Limit) + domain_mem_window_from_to(dev, index++, + pr->Mmio32Base, pr->Mmio32Limit + 1); /* Initialize the system-wide memory resources constraints. */ - if (pr->Mmio64Base <= pr->Mmio64Limit) { - res = new_resource(dev, index++); - res->base = pr->Mmio64Base; - res->limit = pr->Mmio64Limit; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (pr->Mmio64Base <= pr->Mmio64Limit) + domain_mem_window_from_to(dev, index++, + pr->Mmio64Base, pr->Mmio64Limit + 1); } static struct device_operations iio_pcie_domain_ops = { diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 9ed9576..a0babee 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -61,21 +61,11 @@ unsigned int index = 0; - if (mem32_base <= mem32_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem32_base; - res->limit = mem32_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem32_base <= mem32_limit) + domain_mem_window_from_to(domain, index++, mem32_base, mem32_limit + 1); - if (mem64_base <= mem64_limit) { - struct resource *const res = new_resource(domain, index++); - res->base = mem64_base; - res->limit = mem64_limit; - res->size = res->limit - res->base + 1; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; - } + if (mem64_base <= mem64_limit) + domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1); } void create_ioat_domains(const union xeon_domain_path path, -- To view, visit https://review.coreboot.org/c/coreboot/+/82103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Gerrit-Change-Number: 82103 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add domain resource window creation utils
by Arthur Heymans (Code Review) 28 May '24

28 May '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82103?usp=email ) Change subject: soc/intel/xeon_sp: Add domain resource window creation utils ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Gerrit-Change-Number: 82103 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 28 May 2024 09:41:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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