Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82685?usp=email )
Change subject: soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
......................................................................
soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this to 1 is needed to enable HDA audio link.
Same exact situation as with Alder Lake in CL 71715.
Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 2 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/82685/1
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 0c76b7c..7168369 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -247,6 +247,7 @@
uint16_t sata_ports_dito_val[8];
/* Audio related */
+ uint8_t pch_hda_audio_link_hda_enable;
uint8_t pch_hda_dsp_enable;
bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index caf57a3..2bfaed1 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -288,17 +288,11 @@
m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
+ m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;
for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];
- /*
- * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
- * configure GPIO pads for audio. Mainboard is expected to perform all GPIO
- * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
- * configuration for audio pads.
- */
- m_cfg->PchHdaAudioLinkHdaEnable = 0;
memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
--
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Gerrit-Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0
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Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82684?usp=email )
Change subject: soc/intel/mtl/fsp_params.c: Sync Usb4CmMode with Kconfig
......................................................................
soc/intel/mtl/fsp_params.c: Sync Usb4CmMode with Kconfig
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being mismatched.
Same as https://review.coreboot.org/c/coreboot/+/80486 but for Meteor
Lake.
Change-Id: I2c894ecefe06435ca899132c040c8eb68d364443
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/soc/intel/meteorlake/fsp_params.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/82684/1
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index a02d4b9..d472122 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -442,6 +442,8 @@
if (is_dev_enabled(tcss_port_arr[i]))
s_cfg->UsbTcPortEn |= BIT(i);
}
+
+ s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
}
static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
--
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Attention is currently required from: Tim Wawrzynczak.
Elyes Haouas has posted comments on this change by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/50857?usp=email )
Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables
......................................................................
Patch Set 22:
(1 comment)
File src/southbridge/intel/common/rcba_pirq.c:
https://review.coreboot.org/c/coreboot/+/50857/comment/fadcaa30_18eda31a?us… :
PS22, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX);
> They're equivalent
The two calloc calls are not equivalent indeed. The first call, calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX), allocates memory for sizeof(struct slot_pin_irq_map) elements, each of size MAX_SLOTS * PCI_INT_MAX bytes. In contrast, the second call, calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX), allocates memory for MAX_SLOTS elements, each of size sizeof(struct slot_pin_irq_map) * PCI_INT_MAX bytes. Although the total amount of memory allocated is mathematically the same, the second call correctly follows the calloc convention by specifying the number of elements and the size of each element, making it the appropriate and intuitive choice.
(see https://review.coreboot.org/c/coreboot/+/82658)
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Change subject: tree: Use <stdio.h> for snprintf
......................................................................
Patch Set 5: Code-Review+2
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Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82665?usp=email )
Change subject: tree: Use <stdio.h> for snprintf
......................................................................
Patch Set 5:
(1 comment)
File src/device/dram/ddr2.c:
https://review.coreboot.org/c/coreboot/+/82665/comment/4e2f04a5_3cf010ca?us… :
PS5, Line 13: #include <stdio.h>
> This does not seem to be required in this file. […]
Thx
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Attention is currently required from: Maciej Pijanowski, Michał Żygowski.
Hello Maciej Pijanowski, Michał Żygowski, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82673?usp=email
to look at the new patch set (#11).
Change subject: mb/novacustom: add V5x0TU board (Meteor Lake)
......................................................................
mb/novacustom: add V5x0TU board (Meteor Lake)
NovaCustom (Clevo) V5x0TU are two boards with Intel Core Ultra (Meteor
Lake) series processors.
Two variants (V540TU and V560TU) are supported. Their EC firmware is
different due to keyboard layout changes. On coreboot's side, the only
difference are SMBIOS strings.
Working:
- DDR5 SODIMM in slot RAM2
- M.2 2280 PCIe slots
- Thunderbolt, USB ports
- Video outputs in OS and firmware
- I2C touchpad, webcam, SD Card reader
- S0ix
- Booting Ubuntu 24.04 with edk2 UefiPayload
- Vboot, TPM measured boot
Not working:
- DDR5 SODIMM in slot RAM1
- PS/2 keyboard in edk2
- Onboard audio
Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
A src/mainboard/novacustom/Kconfig
A src/mainboard/novacustom/Kconfig.name
A src/mainboard/novacustom/mtl-h/Kconfig
A src/mainboard/novacustom/mtl-h/Kconfig.name
A src/mainboard/novacustom/mtl-h/Makefile.mk
A src/mainboard/novacustom/mtl-h/acpi/backlight.asl
A src/mainboard/novacustom/mtl-h/acpi/mainboard.asl
A src/mainboard/novacustom/mtl-h/board_info.txt
A src/mainboard/novacustom/mtl-h/bootblock.c
A src/mainboard/novacustom/mtl-h/cmos.default
A src/mainboard/novacustom/mtl-h/cmos.layout
A src/mainboard/novacustom/mtl-h/data.vbt
A src/mainboard/novacustom/mtl-h/devicetree.cb
A src/mainboard/novacustom/mtl-h/dsdt.asl
A src/mainboard/novacustom/mtl-h/fadt.c
A src/mainboard/novacustom/mtl-h/gpio.c
A src/mainboard/novacustom/mtl-h/gpio_early.c
A src/mainboard/novacustom/mtl-h/hda_verb.c
A src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h
A src/mainboard/novacustom/mtl-h/ramstage.c
A src/mainboard/novacustom/mtl-h/romstage.c
A src/mainboard/novacustom/mtl-h/vboot-rwab.fmd
22 files changed, 1,401 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/82673/11
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Pranava Y N has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/82637?usp=email )
Change subject: mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports
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Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82637/comment/420af4fa_805c3218?us… :
PS3, Line 9: The devicetree entry and gpio.c updated as per the schematics of Trulo to map the OC fault signals from A0/A1 USB ports.
> wrap up text. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/82637/comment/6ee38b52_3a2375ea?us… :
PS3, Line 11: 335838378
> bug id seems not correct ?
b:335858378 corrected the bug id
https://review.coreboot.org/c/coreboot/+/82637/comment/ef993c8f_aa5d0053?us… :
PS3, Line 12: TEST= NA
> we need a test tag
Acknowledged
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