coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

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3267 discussions

[S] Change in coreboot[main]: arch/arm64: Support FEAT_CCIDX
by Yidi Lin (Code Review) 28 May '24

28 May '24

Attention is currently required from: Julius Werner, Yidi Lin. Hello Eric Lai, Julius Werner, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82635?usp=email to look at the new patch set (#3). Change subject: arch/arm64: Support FEAT_CCIDX ...................................................................... arch/arm64: Support FEAT_CCIDX ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented. If numsets and associativity from CCSIDR_EL1 are not correct, the system would hang during mmu_disable(). Rather than assuming that FEAT_CCIDX is not implemented, this patch adds a check to dcache_apply_all to use the right register format. Reference: - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770 BUG=b:317015456 TEST=mmu_disable works on the FEAT_CCIDX supported SoC. TEST=manually add mmu_disable to emulation/qemu-aarch64/bootblock.c and verify with the command qemu-system-aarch64 -bios \ ./coreboot-builds/EMULATION_QEMU_AARCH64/coreboot.rom -M \ virt,secure=on,virtualization=on -cpu max -cpu cortex-a710 \ -nographic -m 8192M Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/arch/arm64/armv8/cpu.S 1 file changed, 18 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/82635/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c Gerrit-Change-Number: 82635 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Nico Huber (Code Review) 28 May '24

28 May '24

Attention is currently required from: Tim Wawrzynczak. Nico Huber has posted comments on this change by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/50857?usp=email ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 22: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/a9e4344d_de9827f8?us… : PS22, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); > > The two calloc calls are not equivalent indeed. […] Looking at the code, the list is unordered, i.e. not a matrix of MAX_SLOTS x PCI_INT_MAX but just a list of length MAX_SLOTS*PCI_INT_MAX. So IMO Angel is correct, if we bikeshed this, we should do it right, then it would be ``` calloc(MAX_SLOTS * PCI_INT_MAX, sizeof(struct slot_pin_irq_map)) ``` But anyway, before we discuss individual cases, is there any reason we should care for the order of arguments at all? Even the manpage (calloc(3)) says it has two arguments only to make overflows detectable. So the order shouldn't matter, right? Especially not when all the arguments are constants. IMO this discussion is not worth anything for coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/50857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 22 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Tue, 28 May 2024 12:44:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: soc/intel/common/block: move ADL to common descriptor update, enable HAP
by Piotr Kubaj (Code Review) 28 May '24

28 May '24

Piotr Kubaj has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/82418?usp=email ) Change subject: soc/intel/common/block: move ADL to common descriptor update, enable HAP ...................................................................... Abandoned Originally planned changes will be rebased instead of this change -- To view, visit https://review.coreboot.org/c/coreboot/+/82418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I108c53c77d65accc5869ad5019d59def16ffba85 Gerrit-Change-Number: 82418 Gerrit-PatchSet: 4 Gerrit-Owner: Piotr Kubaj <pkubaj(a)anongoth.pl> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[XS] Change in libgfxinit[cros]: gma: Add graphics id for tivviks
by Angel Pons (Code Review) 28 May '24

28 May '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Subrata Banik. Angel Pons has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/libgfxinit/+/82681?usp=email ) Change subject: gma: Add graphics id for tivviks ...................................................................... Patch Set 2: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/libgfxinit/+/82681/comment/3e7e958a_905f2fc3?… : PS2, Line 7: gma: Add graphics id for tivviks : : This patch includes the TWL graphics id for the Tivviks board. Since the IDs (plural: this change adds two IDs) are for TWL (which is used on the tivviks board), I would rephrase the commit message as follows: > gma: Add TWL graphics device IDs > > Add the TWL graphics device IDs for the tivviks board. File common/hw-gfx-gma-config.ads.template: https://review.coreboot.org/c/libgfxinit/+/82681/comment/6f4fd277_ecb5111f?… : PS2, Line 567: Device_Id = 16#46d3# or : Device_Id = 16#46d4# Provided that TWL *is* ADL-N, this is OK. If TWL needs to be handled differently, then these IDs should not be in here. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/82681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: libgfxinit Gerrit-Branch: cros Gerrit-Change-Id: I23a19ab99e1bd1bc88f472116097f364b48d5b79 Gerrit-Change-Number: 82681 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Tue, 28 May 2024 12:24:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: tree: Use Wcalloc-transposed-args command option
by Angel Pons (Code Review) 28 May '24

28 May '24

Attention is currently required from: Elyes Haouas. Angel Pons has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82658?usp=email ) Change subject: tree: Use Wcalloc-transposed-args command option ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/82658/comment/99a4e8c8_07951457?us… : PS3, Line 61: pin_irq_map = calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX); This is still nosense. The function is `void *calloc(size_t num, size_t size)`. The structure is: ``` struct slot_pin_irq_map { unsigned int slot; enum pci_pin pin; /* PIRQ # for PIC mode */ unsigned int pic_pirq; /* GSI # for APIC mode */ unsigned int apic_gsi; }; ``` The variable is declared as follows: ``` struct slot_pin_irq_map *pin_irq_map; ``` So I would say the most semantically correct form would be: ``` pin_irq_map = calloc(MAX_SLOTS * PCI_INT_MAX, sizeof(struct slot_pin_irq_map));``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d Gerrit-Change-Number: 82658 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 28 May 2024 12:23:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Angel Pons (Code Review) 28 May '24

28 May '24

Attention is currently required from: Tim Wawrzynczak. Angel Pons has posted comments on this change by Tim Wawrzynczak. ( https://review.coreboot.org/c/coreboot/+/50857?usp=email ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 22: (1 comment) File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/09488d70_bde77377?us… : PS22, Line 61: pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); > The two calloc calls are not equivalent indeed. The first call, `calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX)`, allocates memory for `sizeof(struct slot_pin_irq_map)` elements, each of size `MAX_SLOTS * PCI_INT_MAX` bytes. In contrast, the second call, `calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX)`, allocates memory for `MAX_SLOTS` elements, each of size `sizeof(struct slot_pin_irq_map) * PCI_INT_MAX` bytes. Although the total amount of memory allocated is mathematically the same, the second call correctly follows the calloc convention by specifying the number of elements and the size of each element, making it the appropriate and intuitive choice. Who said this? It tries to sound convincing, but it's a bunch of nonsense. Also, formatting is messed up (I fixed it in my quote) I said the function calls are equivalent because they allocate the same amount of memory. Changing this won't fix any bugs. But neither of them "follows the calloc convention" (signature is `void *calloc(size_t num, size_t size)`): the `size` parameter would need to be `sizeof(struct slot_pin_irq_map)` or `sizeof(*pin_irq_map)` (the size of one element). > (see https://review.coreboot.org/c/coreboot/+/82658) See reply there. -- To view, visit https://review.coreboot.org/c/coreboot/+/50857?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 22 Gerrit-Owner: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Tue, 28 May 2024 12:23:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports
by Eric Lai (Code Review) 28 May '24

28 May '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, Pranava Y N, Subrata Banik. Eric Lai has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/82637?usp=email ) Change subject: mb/google/brya/variants/trulo: Support OCP fault on A0/1 ports ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82637/comment/08b50a00_041ffb1c?us… : PS4, Line 7: mb/google/brya/variants/trulo Still think it's mb/google/trulo, although the code is in var but this project is the baseboard. -- To view, visit https://review.coreboot.org/c/coreboot/+/82637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Gerrit-Change-Number: 82637 Gerrit-PatchSet: 4 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 May 2024 11:54:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Add WWAN power off sequence
by Eric Lai (Code Review) 28 May '24

28 May '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Leo Chou, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Leo Chou. ( https://review.coreboot.org/c/coreboot/+/82683?usp=email ) Change subject: mb/google/nissa/var/sundance: Add WWAN power off sequence ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Gerrit-Change-Number: 82683 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 28 May 2024 11:51:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: tree: Use <stdio.h> for snprintf
by Yu-Ping Wu (Code Review) 28 May '24

28 May '24

Attention is currently required from: Alexander Couzens, Andrey Petrov, Arthur Heymans, Caveh Jalali, Christian Walter, Cliff Huang, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Forest Mittelberg, Hung-Te Lin, Jason Nien, Johnny Lin, Jonathan Zhang, Julius Werner, Jérémy Compostella, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Martin Roth, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Yidi Lin. Yu-Ping Wu has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82665?usp=email ) Change subject: tree: Use <stdio.h> for snprintf ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Gerrit-Change-Number: 82665 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 28 May 2024 11:05:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up public microcode
by Michał Kopeć (Code Review) 28 May '24

28 May '24

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82686?usp=email ) Change subject: soc/intel/meteorlake: Hook up public microcode ...................................................................... soc/intel/meteorlake: Hook up public microcode Hook up public microcode for stepping C0 / QS. Microcodes for engineering samples are not available, so keep MICROCODE_BLOB_UNDISCLOSED selected for platforms that need it. Change-Id: I16f20956a1490da02acc24156360aef235111494 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/Makefile.mk 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/82686/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index a4ebad4..d7aa13b 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -36,7 +36,6 @@ select INTEL_GMA_OPREGION_2_1 select INTEL_GMA_VERSION_2 select IOAPIC - select MICROCODE_BLOB_UNDISCLOSED select MP_SERVICES_PPI_V2 select MRC_CACHE_USING_MRC_VERSION select MRC_SETTINGS_PROTECT @@ -132,6 +131,7 @@ config SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON bool default n + select MICROCODE_BLOB_UNDISCLOSED help Choose this option if your mainboard has a Meteor Lake pre-production silicon. Typically known as engineering samples (like ES). This type diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk index 893523c..ff2a17f 100644 --- a/src/soc/intel/meteorlake/Makefile.mk +++ b/src/soc/intel/meteorlake/Makefile.mk @@ -60,4 +60,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/meteorlake CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include +# C0 stepping +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-aa-04 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/82686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16f20956a1490da02acc24156360aef235111494 Gerrit-Change-Number: 82686 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

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coreboot-gerrit May 2024