coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/dell: Add Latitude E5520 (Sandybridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/82128?usp=email ) Change subject: mb/dell: Add Latitude E5520 (Sandybridge) ...................................................................... mb/dell: Add Latitude E5520 (Sandybridge) Mainboard is Krug 15". I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A14 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb 7 files changed, 290 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/82128/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 Gerrit-Change-Number: 82128 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6520 (Sandy Bridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/82127?usp=email ) Change subject: mb/dell: Add Latitude E6520 (Sandy Bridge) ...................................................................... mb/dell: Add Latitude E6520 (Sandy Bridge) Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb 7 files changed, 280 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/82127/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec Gerrit-Change-Number: 82127 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6420 (Sandy Bridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/82126?usp=email ) Change subject: mb/dell: Add Latitude E6420 (Sandy Bridge) ...................................................................... mb/dell: Add Latitude E6420 (Sandy Bridge) Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb 7 files changed, 284 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/82126/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 Gerrit-Change-Number: 82126 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/dell: Add Latitude E5530 (Ivy Bridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82125?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/dell: Add Latitude E5530 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E5530 (Ivy Bridge) Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the VBT binary, which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version A21 of the vendor firmware. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb 7 files changed, 288 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82125/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Gerrit-Change-Number: 82125 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6530 (Ivy Bridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Attention is currently required from: Nicholas Chin. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79012?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/dell: Add Latitude E6530 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E6530 (Ivy Bridge) Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was not tested. I do not physically have this system; someone with physical access to one sent me the output of autoport which I then modified to produce this port. I was also sent the vbios obtained using intel_bios_dumper while running version A22 of the vendor firmware, which I then processed using `intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt. This was originally tested and found to be working as a standalone board port in Libreboot, though this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb 7 files changed, 285 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/79012/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Gerrit-Change-Number: 79012 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6430 (Ivy Bridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Attention is currently required from: Martin L Roth, Paul Menzel. Hello Martin L Roth, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77444?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/dell: Add Latitude E6430 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E6430 (Ivy Bridge) Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU was not tested. This is based on the autoport output with some manual fixes. The VBT was obtained using `intelvbttool --inlegacy --outvbt data.vbt` while running version A24 (latest version) of the vendor firmware. The flash is 8MiB + 4MiB, and can be easily accessed by removing the keyboard. It can also be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Working: - Libgfxinit - USB EHCI debug (left side usb port is HCD index 2, middle port on the right side is HCD index 1) with the CH347 - Keyboard - Touchpad/trackpoint - ExpressCard (tested with USB 3.0 card) - Audio - Ethernet - SD card reader - mPCIe WiFi - SeaBIOS 1.16.3 - edk2 (MrChromebox's fork, uefipayload_202309) - Internal flashing using dell-flash-unlock Not working: - S3 suspend: Possibly EC related, DRAM power is getting cut when entering S3 - Physical wireless switch: this triggers an SMI handler in the vendor firmware which sends commands to the EC to enable/disable wireless devices, and has not been reimplemented - Battery reporting: needs ACPI code for the EC - Brightness hotkeys: probably EC related - The system reports that the power button was pressed and shuts down when the CPU hits around 86 degrees Celsius, before the CPU can thermal throttle. Likely EC and possibly PECI related. - Integrated keyboard with upstream GRUB 2.12 payload: Upstream GRUB initializes the 8042 PS/2 controller in a way that is incompatible with how the EC firmware emulates it. GRUB tries to initialize the controller with scan code set 2 without translation, but the EC only ever returns set 1 scan codes to the system and thus is only works as an untranslated set 1 keyboard or a translated set 2 keyboard, regardless of commands to set the scan code. A USB keyboard works fine. Unknown/untested: - Dock - eSATA - TPM - dGPU on non-UMA model - Bluetooth module (not included on my system) [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/dell/snb_ivb_latitude/Kconfig A src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/Makefile.mk A src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl A src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl A src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl A src/mainboard/dell/snb_ivb_latitude/acpi_tables.c A src/mainboard/dell/snb_ivb_latitude/board_info.txt A src/mainboard/dell/snb_ivb_latitude/cmos.default A src/mainboard/dell/snb_ivb_latitude/cmos.layout A src/mainboard/dell/snb_ivb_latitude/devicetree.cb A src/mainboard/dell/snb_ivb_latitude/dsdt.asl A src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads A src/mainboard/dell/snb_ivb_latitude/mainboard.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb 19 files changed, 607 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/77444/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/77444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Gerrit-Change-Number: 77444 Gerrit-PatchSet: 11 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Iru Cai <mytbk920423(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage
by Tim Van Patten (Code Review) 01 May '24

01 May '24

Attention is currently required from: Andrey Petrov, Karthik Ramasubramanian, Matt DeVillier, Ronak Kanabar, Subrata Banik. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82121?usp=email ) Change subject: drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/82121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Gerrit-Change-Number: 82121 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 01 May 2024 19:45:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage
by Karthik Ramasubramanian (Code Review) 01 May '24

01 May '24

Attention is currently required from: Andrey Petrov, Matt DeVillier, Ronak Kanabar, Subrata Banik, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82121?usp=email ) Change subject: drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > > > what if any platform decide to not call into fsp notify phases like intel platform starting from […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Gerrit-Change-Number: 82121 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 01 May 2024 19:05:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage
by Karthik Ramasubramanian (Code Review) 01 May '24

01 May '24

Attention is currently required from: Andrey Petrov, Karthik Ramasubramanian, Matt DeVillier, Ronak Kanabar, Tim Van Patten. Hello Andrey Petrov, Matt DeVillier, Ronak Kanabar, Subrata Banik, Tim Van Patten, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82121?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage ...................................................................... drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stage bmp_load_logo() loads the custom logo.bmp file into CBMEM. This cbmem buffer is released after FSP-S init is complete. In certain platforms, the logo file is displayed during PCI enumeration. This means the logo buffer is used after it is released. Fix this issue by releasing the logo buffer when the coreboot has finished loading payload. During S3 scenario CBMEM is locked, bmp logo is not loaded and hence the release is a no-op. BUG=b:337144954 TEST=Build Skyrim BIOS Image and boot to OS. Ensure that the chromeOS boot logo is seen without any corruption. Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/82121/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Gerrit-Change-Number: 82121 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/mtlrvp: use different names for mtlrvp variants
by Miguel Quintero (Code Review) 01 May '24

01 May '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Subrata Banik, YH Lin. Miguel Quintero has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82084?usp=email ) Change subject: soc/intel/mtlrvp: use different names for mtlrvp variants ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Do you see any abnormal reboot issue w/ this CL due to crash in BT stack after booting to OS. I haven't had any issues with this firmware. What issues are you getting? -- To view, visit https://review.coreboot.org/c/coreboot/+/82084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a Gerrit-Change-Number: 82084 Gerrit-PatchSet: 5 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Miguel Quintero <miguelquintero(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 01 May 2024 16:30:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2024