coreboot-gerrit May 2024

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[S] Change in coreboot[main]: mb/google/nissa: Create a riven variant
by Eric Lai (Code Review) 02 May '24

02 May '24

Attention is currently required from: David Wu, Dinesh Gehlot, Morris Hsu, Nick Vaccaro, Ren Kuo, Subrata Banik, Tyler Wang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82132?usp=email ) Change subject: mb/google/nissa: Create a riven variant ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b Gerrit-Change-Number: 82132 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 May 2024 00:51:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
by Eric Lai (Code Review) 02 May '24

02 May '24

Attention is currently required from: Dinesh Gehlot, Emilie Roberts, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, Won Chung. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81354?usp=email ) Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: please rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/81354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875 Gerrit-Change-Number: 81354 Gerrit-PatchSet: 5 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Emilie Roberts <hadrosaur(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benson Leung <bleung(a)google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prashant Malani <pmalani(a)chromium.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Emilie Roberts <hadrosaur(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 02 May 2024 00:49:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/pujjoga: Add GPIO table
by Eric Lai (Code Review) 02 May '24

02 May '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82044?usp=email ) Change subject: mb/google/brya/var/pujjoga: Add GPIO table ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99 Gerrit-Change-Number: 82044 Gerrit-PatchSet: 9 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 May 2024 00:47:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/drallion: make use of chipset devicetree
by Felix Singer (Code Review) 02 May '24

02 May '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82155?usp=email ) Change subject: mb/google/drallion: make use of chipset devicetree ...................................................................... mb/google/drallion: make use of chipset devicetree Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/82155/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index fb2389c..86aab95 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -217,7 +217,7 @@ register "gpio_pm[COMM_4]" = "0" device domain 0 on - device pci 02.0 on + device ref igpu on chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD0"" @@ -231,16 +231,16 @@ register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" device generic 0 on end end - end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 13.0 on # Integrated Sensor Hub + end + device ref dptf on end + device ref thermal on end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""drallion_ish.bin"" device generic 0 on end end end - device pci 14.0 on + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -316,14 +316,14 @@ end end end - end # USB xHCI - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" @@ -383,8 +383,8 @@ register "device_present_gpio_invert" = "1" device i2c 34 on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -399,29 +399,29 @@ register "detect" = "1" device i2c 15 on end end - end # I2C #1 - device pci 19.0 on + end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 1d.0 on + end + device ref pcie_rp9 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" - end # PCI Express Port 9 - device pci 1d.4 on + end + device ref pcie_rp13 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 on end # UART #0 - device pci 1f.0 on + end + device ref uart0 on end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + end + device ref hda on end + device ref smbus on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/82155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9 Gerrit-Change-Number: 82155 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/drallion: Remove settings equal to chipset dt
by Felix Singer (Code Review) 02 May '24

02 May '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82154?usp=email ) Change subject: mb/google/drallion: Remove settings equal to chipset dt ...................................................................... mb/google/drallion: Remove settings equal to chipset dt Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 0 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/82154/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d6200d9..fb2389c 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -216,9 +216,7 @@ register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge device pci 02.0 on chip drivers/gfx/generic register "device_count" = "1" @@ -236,8 +234,6 @@ end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 device pci 13.0 on # Integrated Sensor Hub chip drivers/intel/ish register "firmware_name" = ""drallion_ish.bin"" @@ -321,14 +317,12 @@ end end end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) device pci 14.3 on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end end # CNVi wifi - device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" @@ -406,15 +400,6 @@ device i2c 15 on end end end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA device pci 19.0 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -422,42 +407,21 @@ device i2c 50 on end end end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" end # PCI Express Port 13 (x4) device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 device pci 1f.0 on chip ec/google/wilco device pnp 0c09.0 on end end end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE end end -- To view, visit https://review.coreboot.org/c/coreboot/+/82154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011 Gerrit-Change-Number: 82154 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Override TDP PL1 value
by SH Kim (Code Review) 02 May '24

02 May '24

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82151?usp=email ) Change subject: mb/google/brya/var/xol: Override TDP PL1 value ...................................................................... mb/google/brya/var/xol: Override TDP PL1 value Update TDP PL1 value for the DTT optimization. The new value 18W is from internal thermal/performance team. - tdp_pl1_override: 15 -> 18 (W) BUG=b:336684032 BRANCH=brya TEST=built and verified MSR PL1 value. Intel doc #614179 introduces how to check current PL values. [Original MSR PL1/PL2/PL4 register values for xol] cd /sys/class/powercap/intel-rapl/intel-rapl\:0/ grep . *power_limit* constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W) constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W) constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W) After this patch: constraint_0_power_limit_uw:18000000 constraint_1_power_limit_uw:55000000 constraint_2_power_limit_uw:114000000 Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xol/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/82151/1 diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 80d15fe..fe145ea 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -25,6 +25,12 @@ # display flickering issue. register "disable_dynamic_tccold_handshake" = "true" + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + register "tcc_offset" = "6" # TCC of 94 register "platform_pmax" = "122" -- To view, visit https://review.coreboot.org/c/coreboot/+/82151?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f Gerrit-Change-Number: 82151 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/common: Make use of is_devfn_enabled()
by Felix Singer (Code Review) 02 May '24

02 May '24

Attention is currently required from: Felix Singer. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82119?usp=email to look at the new patch set (#4). Change subject: soc/intel/common: Make use of is_devfn_enabled() ...................................................................... soc/intel/common: Make use of is_devfn_enabled() Using is_devfn_enabled() cleans up some code and even makes the method is_graphics_disabled() superfluous. Change-Id: I6e3dcc456d56b35c94c226ade0414e5c94d4c641 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c 3 files changed, 4 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/82119/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82119?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e3dcc456d56b35c94c226ade0414e5c94d4c641 Gerrit-Change-Number: 82119 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/common: Make use of is_devfn_enabled()
by Felix Singer (Code Review) 02 May '24

02 May '24

Attention is currently required from: Felix Singer. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82119?usp=email ) Change subject: soc/intel/common: Make use of is_devfn_enabled() ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82119?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e3dcc456d56b35c94c226ade0414e5c94d4c641 Gerrit-Change-Number: 82119 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 02 May 2024 00:18:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Clean up device enablement configuration
by Matt DeVillier (Code Review) 02 May '24

02 May '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82120?usp=email ) Change subject: soc/intel/xeon_sp: Clean up device enablement configuration ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82120?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493 Gerrit-Change-Number: 82120 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 02 May 2024 00:03:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cannonlake: Clean up device enablement configuration
by Matt DeVillier (Code Review) 02 May '24

02 May '24

Attention is currently required from: Felix Singer. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82118?usp=email ) Change subject: soc/intel/cannonlake: Clean up device enablement configuration ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094 Gerrit-Change-Number: 82118 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 02 May 2024 00:00:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2024