coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: Haswell NRI: Implement fast boot path
by Angel Pons (Code Review) 02 May '24

02 May '24

Attention is currently required from: Arthur Heymans, Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81897?usp=email ) Change subject: Haswell NRI: Implement fast boot path ...................................................................... Patch Set 1: -Code-Review (1 comment) Patchset: PS1: > Something seems wrong in the fast boot path, I can reach the payload but booting from a SATA SSD is […] False alarm, it was a problem with the board I was testing things with: CB:68188 -- To view, visit https://review.coreboot.org/c/coreboot/+/81897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6 Gerrit-Change-Number: 81897 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 May 2024 23:59:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Angel Pons (Code Review) 02 May '24

02 May '24

Attention is currently required from: Nicholas Sudsgaard. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email ) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... Patch Set 27: (1 comment) File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80343/comment/de01d5c9_d4525aea : PS27, Line 12: register "PcieRpClkReqSupport[0]" = "true" : register "PcieRpClkReqNumber[0]" = "2" : register "PcieRpClkSrcNumber[0]" = "0" > Uh, this is a CPU RP, not a PCH RP. […] Actually, I don't think Kaby Lake FSP exposes any UPDs for this... -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 27 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Wed, 01 May 2024 23:52:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Angel Pons (Code Review) 02 May '24

02 May '24

Attention is currently required from: Nicholas Sudsgaard. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email ) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... Patch Set 27: (1 comment) File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80343/comment/ec7e1a48_a3b9578f : PS27, Line 12: register "PcieRpClkReqSupport[0]" = "true" : register "PcieRpClkReqNumber[0]" = "2" : register "PcieRpClkSrcNumber[0]" = "0" > I just checked. The UPDs are hooked up to these settings. They just have the same name. […] Uh, this is a CPU RP, not a PCH RP. I'm pretty sure the CPU RP UPDs aren't exposed as devicetree settings on Skylake. -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 27 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Wed, 01 May 2024 23:48:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brya/var/xol: Tune I2C5 timing parameters
by SH Kim (Code Review) 02 May '24

02 May '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82100?usp=email ) Change subject: mb/google/brya/var/xol: Tune I2C5 timing parameters ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Ping for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/82100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3 Gerrit-Change-Number: 82100 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 01 May 2024 23:47:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Felix Singer (Code Review) 02 May '24

02 May '24

Attention is currently required from: Nicholas Sudsgaard. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email ) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... Patch Set 27: (1 comment) File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80343/comment/dfa54380_02efaf10 : PS27, Line 12: register "PcieRpClkReqSupport[0]" = "true" : register "PcieRpClkReqNumber[0]" = "2" : register "PcieRpClkSrcNumber[0]" = "0" > I think the FSP UPDs exist, but they may not be exposed as devicetree settings. I just checked. The UPDs are hooked up to these settings. They just have the same name. Is that why you think they are not hooked up? -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 27 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Wed, 01 May 2024 23:46:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/asrock/z97_extreme6: Add new mainboard
by Angel Pons (Code Review) 02 May '24

02 May '24

Attention is currently required from: Felix Singer, Martin L Roth, Nico Huber, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68188?usp=email ) Change subject: mb/asrock/z97_extreme6: Add new mainboard ...................................................................... Patch Set 9: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68188/comment/e2a6d383_bf3d12eb : PS8, Line 51: - Flashing with flashrom > It's probably out of sync. […] Done File src/mainboard/asrock/z97_extreme6/bootblock.c: https://review.coreboot.org/c/coreboot/+/68188/comment/d2e8a203_d1e09a92 : PS8, Line 11: PP_OD_DEV > Maybe not the best choice of names as there is also a parallel port (PP) device. […] This name comes from `NCT6791D_GPIO_PP_OD`, so maybe I can throw in a `GPIO_` prefix. I will add a comment there anyway. https://review.coreboot.org/c/coreboot/+/68188/comment/f4d3e5f4_774e399b : PS8, Line 18: pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); > Bits 2..1 suggest pin 51 is MSDA, but WLAN1_ON/OFF in boardview. Fixed, can't test at the moment though. https://review.coreboot.org/c/coreboot/+/68188/comment/9d07b285_f4488dbd : PS8, Line 18: pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); > Meh, bit 5 is reserved in my ds. Same. I chose to keep it like this because it's the default value. https://review.coreboot.org/c/coreboot/+/68188/comment/70659e01_e3b786ff : PS8, Line 18: pnp_write_config(GLOBAL_DEV, 0x1b, 0xf0); > Bit 4 sets pin 95 to CIRRX? But CIR is disabled in the DT. Boardview says DEVSLP for SATAE_1. Decided not to set the bit even though I can't test. https://review.coreboot.org/c/coreboot/+/68188/comment/ab060ef6_11881665 : PS8, Line 33: pnp_write_config(ACPI_DEV, 0xe4, 0x70); > This also seems to set "User defined mode for power loss last-state. (The last- […] It's copied from B85M Pro4, which in turn copied it from H81M-HDS. So it's probably wrong. I'll use 0x10 instead. S3 suspend/resume still works. File src/mainboard/asrock/z97_extreme6/devicetree.cb: https://review.coreboot.org/c/coreboot/+/68188/comment/300471be_8fd79d82 : PS8, Line 20: Bifurcable > If the verb is 'bifurcate', this would be 'bifurcatable' right? Oops. Reworded this (I saw the mux spam should just work) -- To view, visit https://review.coreboot.org/c/coreboot/+/68188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Gerrit-Change-Number: 68188 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 May 2024 23:40:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/asrock/z97_extreme6: Add new mainboard
by Angel Pons (Code Review) 02 May '24

02 May '24

Attention is currently required from: Felix Singer, Martin L Roth, Nico Huber, Paul Menzel. Hello Felix Singer, Nico Huber, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68188?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: mb/asrock/z97_extreme6: Add new mainboard ...................................................................... mb/asrock/z97_extreme6: Add new mainboard That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits. This board has two socketed DIP-8 SPI flash chips and a physical switch to choose which one should the system boot from. As long as one of them contains a bootable firmware image, it is possible to reflash the other chip using the internal programmer by flipping the switch after booting to OS. Even if one somehow manages to flash unbootable firmware to both chips, they are socketed: one can carefully remove them from the socket and reflash them externally, which is a relatively safe procedure (when compared to in-circuit flashing, especially if the board isn't designed to safely be flashed in-circuit). In short, the board is hard to brick. Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe it's something about RcvEn, but it's unlikely it can easily be fixed. Working: - All four DIMM slots - Broadwell MRC.bin for raminit purposes - Serial port to emit spam - POST code display - S3 suspend/resume - All rear USB 3.0 ports - Internal USB 2.0 port - Audio output (green jack) - Integrated graphics (libgfxinit) - HDMI - VBT - Intel GbE (I218-V PHY and PCH MAC) - Realtek RTL8111E GbE - At least one SATA port - M2_1 slot (Gen3 x4) - Flashing internally with flashrom - SeaBIOS (current version) to boot Arch Linux - NCT6791D Super I/O software-based fan control tested using `sensors` and `pwmconfig`, all 6 fan tachometers and 5 PWM outputs work fine. Untested for now (i.e. should work, will eventually test): - DVI-I, DisplayPort - EHCI debug - Front USB 2.0 and 3.0 ports - The other audio jacks (as well as SPDIF) - The other PCIe and M.2 ports - Non-Linux OSes - PS/2 combo port (can only test with a keyboard) Untestable (i.e. cannot test due to unavailable hardware): - Thunderbolt AIC (Add-In Card) support Not working: - Broadwell CPUs, they require more magic to work. - Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were not tested. It seems that the problem is with the controllers. - Super I/O automatic fan control: not yet implemented in coreboot. To control fans, use software fan control methods in the meantime. - Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor, connected to the board's HDMI output says "Unsupported resolution" after libgfxinit configured the iGPU outputs in linear framebuffer mode. HDMI output works fine after Linux's i915 driver takes over. Not sure if it's specific to the monitor: the HDMI cable is beaten up, and it is hard to replace (need to relocate the logic board so that the ports are accessible). Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/z97_extreme6/Kconfig A src/mainboard/asrock/z97_extreme6/Kconfig.name A src/mainboard/asrock/z97_extreme6/Makefile.mk A src/mainboard/asrock/z97_extreme6/acpi/ec.asl A src/mainboard/asrock/z97_extreme6/acpi/platform.asl A src/mainboard/asrock/z97_extreme6/acpi/superio.asl A src/mainboard/asrock/z97_extreme6/board_info.txt A src/mainboard/asrock/z97_extreme6/bootblock.c A src/mainboard/asrock/z97_extreme6/data.vbt A src/mainboard/asrock/z97_extreme6/devicetree.cb A src/mainboard/asrock/z97_extreme6/dsdt.asl A src/mainboard/asrock/z97_extreme6/gma-mainboard.ads A src/mainboard/asrock/z97_extreme6/gpio.c A src/mainboard/asrock/z97_extreme6/hda_verb.c A src/mainboard/asrock/z97_extreme6/romstage.c 15 files changed, 619 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/68188/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/68188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9 Gerrit-Change-Number: 68188 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6430 (Ivy Bridge)
by Felix Singer (Code Review) 02 May '24

02 May '24

Attention is currently required from: Martin L Roth, Nicholas Chin, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77444?usp=email ) Change subject: mb/dell: Add Latitude E6430 (Ivy Bridge) ...................................................................... Patch Set 12: (1 comment) File src/mainboard/dell/snb_ivb_latitude/devicetree.cb: https://review.coreboot.org/c/coreboot/+/77444/comment/8f31290b_dc48ddbd : PS12, Line 4: register "gfx" = "GMA_STATIC_DISPLAYS(1)" : register "gpu_dp_b_hotplug" = "4" : register "gpu_dp_c_hotplug" = "4" : register "gpu_dp_d_hotplug" = "4" : register "gpu_panel_port_select" = "0" : register "gpu_panel_power_backlight_off_delay" = "2300" : register "gpu_panel_power_backlight_on_delay" = "2300" : register "gpu_panel_power_cycle_delay" = "6" : register "gpu_panel_power_down_delay" = "400" : r Move into igpu device scope -- To view, visit https://review.coreboot.org/c/coreboot/+/77444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Gerrit-Change-Number: 77444 Gerrit-PatchSet: 12 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Iru Cai <mytbk920423(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 01 May 2024 23:26:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: libpayload: Support choosing fmap partitions
by Vladimir Serbinenko (Code Review) 02 May '24

02 May '24

Attention is currently required from: Julius Werner. Vladimir Serbinenko has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81899?usp=email ) Change subject: libpayload: Support choosing fmap partitions ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I assume this is part of your boot path picker payload effort... […] Yes, it's for boot path picker. ro_load is not enough because I actually need the opposite: to switch from RO to a chosen RW partition -- To view, visit https://review.coreboot.org/c/coreboot/+/81899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie191b7003a2d9a2220bc27712ea9cb9434cf8d28 Gerrit-Change-Number: 81899 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 May 2024 22:45:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6530 (Ivy Bridge)
by Felix Singer (Code Review) 02 May '24

02 May '24

Attention is currently required from: Nicholas Chin, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79012?usp=email ) Change subject: mb/dell: Add Latitude E6530 (Ivy Bridge) ...................................................................... Patch Set 3: (1 comment) File src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79012/comment/f939145d_c0e8d281 : PS3, Line 11: register "superspeed_capable_ports" = "0x0000000f" : register "xhci_overcurrent_mapping" = "0x00000c03" : Move into xhci device scope -- To view, visit https://review.coreboot.org/c/coreboot/+/79012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Gerrit-Change-Number: 79012 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 01 May 2024 22:07:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2024