coreboot-gerrit May 2024

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[L] Change in coreboot[main]: mb/system76/rpl: Add Adder WS 4 as a variant
by Tim Crawford (Code Review) 21 May '24

21 May '24

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82595?usp=email ) Change subject: mb/system76/rpl: Add Adder WS 4 as a variant ...................................................................... mb/system76/rpl: Add Adder WS 4 as a variant The Adder WS 4 (addw4) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSDs - All … [View More]USB ports - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 Not working: - Discrete/Hybrid graphics - Detection of devices in TBT slot on boot Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/rpl/Kconfig M src/mainboard/system76/rpl/Kconfig.name M src/mainboard/system76/rpl/devicetree.cb A src/mainboard/system76/rpl/variants/addw4/board.fmd A src/mainboard/system76/rpl/variants/addw4/board_info.txt A src/mainboard/system76/rpl/variants/addw4/data.vbt A src/mainboard/system76/rpl/variants/addw4/gpio.c A src/mainboard/system76/rpl/variants/addw4/gpio_early.c A src/mainboard/system76/rpl/variants/addw4/hda_verb.c A src/mainboard/system76/rpl/variants/addw4/overridetree.cb A src/mainboard/system76/rpl/variants/addw4/romstage.c 11 files changed, 523 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/82595/1 diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index 60ea71b..e727abd 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -32,6 +32,12 @@ select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE_PCH_S +config BOARD_SYSTEM76_ADDW4 + select BOARD_SYSTEM76_RPL_COMMON + select EC_SYSTEM76_EC_DGPU + select PCIEXP_HOTPLUG + select SOC_INTEL_ALDERLAKE_PCH_S + config BOARD_SYSTEM76_BONW15 select BOARD_SYSTEM76_RPL_COMMON select EC_SYSTEM76_EC_DGPU @@ -78,6 +84,7 @@ config VARIANT_DIR default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 @@ -91,6 +98,7 @@ config MAINBOARD_PART_NUMBER default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 @@ -100,7 +108,7 @@ default "serw13" if BOARD_SYSTEM76_SERW13 config MAINBOARD_SMBIOS_PRODUCT_NAME - default "Adder WS" if BOARD_SYSTEM76_ADDW3 + default "Adder WS" if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 default "Bonobo WS" if BOARD_SYSTEM76_BONW15 default "Darter Pro" if BOARD_SYSTEM76_DARP9 default "Galago Pro" if BOARD_SYSTEM76_GALP7 @@ -111,6 +119,7 @@ config MAINBOARD_VERSION default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index da5d400..64c4ceb 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -3,6 +3,9 @@ config BOARD_SYSTEM76_ADDW3 bool "addw3" +config BOARD_SYSTEM76_ADDW4 + bool "addw3" + config BOARD_SYSTEM76_BONW15 bool "bonw15" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index d389d21..4fd50fd 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -53,7 +53,7 @@ register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 # FIXME: DevSlp breaks S0ix - #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + #register "sata_ports_dev_slp[1]" = "1" end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel diff --git a/src/mainboard/system76/rpl/variants/addw4/board.fmd b/src/mainboard/system76/rpl/variants/addw4/board.fmd new file mode 100644 index 0000000..b2615d1 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 3944K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/addw4/board_info.txt b/src/mainboard/system76/rpl/variants/addw4/board_info.txt new file mode 100644 index 0000000..01f9c50 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/board_info.txt @@ -0,0 +1,2 @@ +Board name: addw4 +Release year: 2024 diff --git a/src/mainboard/system76/rpl/variants/addw4/data.vbt b/src/mainboard/system76/rpl/variants/addw4/data.vbt new file mode 100644 index 0000000..40fdfb2 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/data.vbt Binary files differ diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio.c b/src/mainboard/system76/rpl/variants/addw4/gpio.c new file mode 100644 index 0000000..471212b --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/gpio.c @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVVDD_EN_R + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, NONE), + PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE# + PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT# + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3 + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal freq strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS confidentiality strap + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // I2C2_SDA (Pantone) + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // I2C2_SCL (Pantone) + PAD_NC(GPP_C5, NONE), // eSPI disable strap + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // SMD_7411 + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // SMC_7411 + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_NC(GPP_C9, NONE), + PAD_CFG_GPO(GPP_C10, 0, DEEP), // TEST_R (ANX7411) + PAD_CFG_GPO(GPP_C11, 0, DEEP), // PCH_TEST_R_2 (ANX7411) + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_2 + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_2 + // GPP_C20 (UART2_RXD) configured in bootblock + // GPP_C21 (UART2_TXD) configured in bootblock + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP + PAD_NC(GPP_D4, NONE), + PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N + // GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + // GPP_D12 (SSD2_CLKREQ#) configured by FSP + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI# + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3# + PAD_NC(GPP_E13, NONE), + PAD_NC(GPP_E14, NONE), + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // M.2_SSD_SATA_DET_N + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD_SATA_DEVSLP + PAD_NC(GPP_F6, NONE), + _PAD_CFG_STRUCT(GPP_F7, 0x80100100, 0x0000), // 7411_INTP_OUT + PAD_NC(GPP_F8, NONE), + // GPP_F9 (DGPU_PWR_EN) configured in bootblock + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // Recovery strap + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N + _PAD_CFG_STRUCT(GPP_F16, 0x80100100, 0x0000), // INTP_OUT + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP# + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 0, DEEP), // Board ID 2 + PAD_CFG_GPO(GPP_G1, 0, DEEP), // Board ID 3 + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPI(GPP_G3, NONE, DEEP), // MB detect GN20/GN21 + PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Board ID 1 + PAD_NC(GPP_G5, NONE), + PAD_CFG_GPI(GPP_G6, NONE, DEEP), // MB detect G-SYNC + PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MB detect 230W/180W adapter + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP + PAD_CFG_GPO(GPP_H1, 0, DEEP), // Pantone detect + PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_GPIO_WAKE_N + // GPP_H3 (NC) configured by FSP + // GPP_H4 (SSD1_SATA_CLKREQ#) configured by FSP + // GPP_H5 (WLAN_CLKREQ#) configured by FSP + // GPP_H6 (NC) configured by FSP + // GPP_H7 (LAN_CLKREQ#) configured by FSP + // GPP_H8 (PEG_CLKREQ#) configured by FSP + // GPP_H9 (SSD3_CLKREQ#) configured by FSP + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT strap + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_CFG_GPO(GPP_H18, 0, DEEP), // 1.8V VCCPSPI strap + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // DP_HPD + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // HDMI_HPD + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // USB_OC4# + PAD_CFG_GPI(GPP_I12, NONE, DEEP), // USB_OC5# + PAD_CFG_GPI(GPP_I13, NONE, DEEP), // USB_OC6# + PAD_CFG_GPI(GPP_I14, NONE, DEEP), // USB_OC7# + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_CFG_GPO(GPP_I18, 0, DEEP), // No reboot strap + PAD_NC(GPP_I19, NONE), + PAD_NC(GPP_I20, NONE), + PAD_NC(GPP_I21, NONE), + PAD_CFG_GPO(GPP_I22, 0, DEEP), // Boot BIOS strap + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R / Xtal freq strap + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R / M.2 CNV modes strap + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU + PAD_NC(GPP_J9, NONE), + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_NC(GPP_K3, NONE), + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + // GPP_K6 not in schematics + // GPP_K7 not in schematics + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_K10 not in schematics + PAD_NC(GPP_K11, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD + PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_R10, NONE), + PAD_NC(GPP_R11, NONE), + PAD_NC(GPP_R12, NONE), + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + // GPP_R16 (DGPU_RST#_PCH) configured in bootblock + PAD_NC(GPP_R17, NONE), + PAD_NC(GPP_R18, NONE), + PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI# + PAD_NC(GPP_R20, NONE), + PAD_NC(GPP_R21, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio_early.c b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c new file mode 100644 index 0000000..b6914ad --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/addw4/hda_verb.c b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c new file mode 100644 index 0000000..3850d34 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x15580353, /* Subsystem ID */ + 35, /* Number of entries */ + + 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, + + AZALIA_SUBVENDOR(0, 0x15580353), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, + 0x0205004a, 0x02042010, 0x02050038, 0x02047909, + 0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82, + 0x05350000, 0x0534201a, 0x05350000, 0x0534201a, + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, + 0x05350003, 0x05341ec4, 0x05350004, 0x05340000, + 0x05450000, 0x05442000, 0x0545001d, 0x05440800, + 0x0545001e, 0x05440800, 0x05450003, 0x05441ec4, + 0x05450004, 0x05440000, 0x05350000, 0x0534a01a, + 0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135, + 0x02050040, 0x02048800, 0x05a50001, 0x05a4001f, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, + 0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390, + 0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00, + 0x00170500, 0x00170500, 0x05a50004, 0x05a40113, + 0x02050008, 0x02046a8c, 0x02050076, 0x0204f000, + 0x0205000e, 0x020465c0, 0x02050033, 0x02048580, + 0x02050069, 0x0204fda8, 0x02050068, 0x02040000, + 0x02050003, 0x02040002, 0x02050069, 0x02040000, + 0x02050068, 0x02040001, 0x0205002e, 0x0204290e, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/addw4/overridetree.cb b/src/mainboard/system76/rpl/variants/addw4/overridetree.cb new file mode 100644 index 0000000..0fdde89 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/overridetree.cb @@ -0,0 +1,101 @@ +chip soc/intel/alderlake + # Support 5600 MT/s memory + register "max_dram_speed_mts" = "5600" + + device domain 0 on + subsystemid 0x1558 0x0353 inherit + + device ref xhci on + register "usb2_ports" = "{ + /* Port reset messaging cannot be used, + * so do not use USB2_PORT_TYPE_C for these */ + [0] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */ + [1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC2 */ + [2] = USB2_PORT_MID(OC_SKIP), /* J_USB2 */ + [3] = USB2_PORT_MID(OC_SKIP), /* J_USB1 (Audio board) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ + [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB2 */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB1 (Audio board) */ + }" + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + + device ref pcie5_0 on + # DGPU + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 14, + .clk_req = 14, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref pcie_rp3 on + # GLAN + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 13, + .clk_req = 13, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end # Realtek RTL8111H + end + device ref pcie_rp8 on + # WLAN + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 11, + .clk_req = 11, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp13 on + # J_SSD1 + register "pch_pcie_rp[PCH_RP(13)]" = "{ + .clk_src = 10, + .clk_req = 10, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp21 on + # J_SSD2 + register "pch_pcie_rp[PCH_RP(21)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp25 on + # J_SSD3 + register "pch_pcie_rp[PCH_RP(25)]" = "{ + .clk_src = 15, + .clk_req = 15, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + end +end diff --git a/src/mainboard/system76/rpl/variants/addw4/romstage.c b/src/mainboard/system76/rpl/variants/addw4/romstage.c new file mode 100644 index 0000000..fe91032 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/romstage.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + .ddr_config = { + .dq_pins_interleaved = true, + }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to hybrid graphics + mupd->FspmConfig.PrimaryDisplay = 4; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Gerrit-Change-Number: 82595 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> [View Less]

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[S] Change in coreboot[main]: crossgcc: Update LLVM from 18.1.5 to 18.1.6
by 9elements QA (Code Review) 21 May '24

21 May '24

9elements QA has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82552?usp=email ) Change subject: crossgcc: Update LLVM from 18.1.5 to 18.1.6 ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/208395 PASS: x86_32 "Hermes … [View More]CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/208393 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/208392 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/208391 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/208390 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/208389 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/208388 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/208387 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/208386 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/208385 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/208384 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/208383 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/82552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie087f43e6f60df7b97d7d7b402d3540c3a0a2461 Gerrit-Change-Number: 82552 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 21 May 2024 21:07:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No [View Less]

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[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
by Brandon Weeks (Code Review) 21 May '24

21 May '24

Attention is currently required from: Angel Pons, Federico Amedeo Izzo, Felix Singer, Joel Linn, Paul Menzel. Brandon Weeks has posted comments on this change by Brandon Weeks. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board ...................................................................... Patch Set 10: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81595/comment/983288b3_7bc2795e?us… : PS9, … [View More]

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[L] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
by Brandon Weeks (Code Review) 21 May '24

21 May '24

Attention is currently required from: Angel Pons, Brandon Weeks, Federico Amedeo Izzo, Felix Singer, Joel Linn, Paul Menzel. Hello Angel Pons, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81595?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: mb/… [View More]cwwk: Add CWWK CW-ADL-4L-V1.0 board ...................................................................... mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE ports, similar boards are available in other port configurations. As a low cost, relatively high performance board with 4 NICs, it is well suited for networking or 'homelab' tasks. CPU: Intel N100 or N350 Memory: DDR5-4800 SODIMM (max 16 GB) NIC: 4x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 4x Ethernet - Display Port - HDMI - 4x USB 2.0 - Micro SD Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - DisplayPort / HDMI - 4x Intel I226 2.5 GbE NICs - M.2 ports - Micro SD slot Not working / not tested: - Fan (ITE IT8613E) - Audio - ACPI S3 / S0ix - Internal USB ports VBT extracted from vendor UEFI firmware version ADLN 0.01 x64 (04/04/2023 11:42:38). Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Signed-off-by: Brandon Weeks <me(a)brandonweeks.com> --- A src/mainboard/cwwk/Kconfig A src/mainboard/cwwk/Kconfig.name A src/mainboard/cwwk/adl/Kconfig A src/mainboard/cwwk/adl/Kconfig.name A src/mainboard/cwwk/adl/Makefile.mk A src/mainboard/cwwk/adl/board_info.txt A src/mainboard/cwwk/adl/bootblock.c A src/mainboard/cwwk/adl/data.vbt A src/mainboard/cwwk/adl/devicetree.cb A src/mainboard/cwwk/adl/dsdt.asl A src/mainboard/cwwk/adl/gpio.h A src/mainboard/cwwk/adl/mainboard.c A src/mainboard/cwwk/adl/romstage_fsp_params.c 13 files changed, 521 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81595/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be Gerrit-Change-Number: 81595 Gerrit-PatchSet: 10 Gerrit-Owner: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-CC: Matthew Garrett <mjgarrett59(a)googlemail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> [View Less]

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[XS] Change in coreboot[main]: mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<'
by Elyes Haouas (Code Review) 21 May '24

21 May '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Elyes Haouas has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82579?usp=email ) Change subject: mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82579?usp=email To unsubscribe, or for help … [View More]

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 21 May '24

21 May '24

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/81968?usp=email ) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... Patch Set 68: (1 comment) File payloads/libpayload/arch/x86/pt.S: https://review.coreboot.org/c/coreboot/+/81968/comment/0ce77e7c_5057cbbd?us… : PS64, … [View More]

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 21 May '24

21 May '24

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81968?usp=email to look at the new patch set (#68). Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... libpayload: Add x86_64 (64-bit) support This patch introduces x86_64 (64-bit) support to the payload, … [View More]building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.mk M payloads/libpayload/arch/x86/Makefile.mk M payloads/libpayload/arch/x86/exception.c A payloads/libpayload/arch/x86/exception_asm_64.S R payloads/libpayload/arch/x86/exec.c M payloads/libpayload/arch/x86/gdb.c A payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/libpayload.ldscript A payloads/libpayload/arch/x86/pt.S M payloads/libpayload/arch/x86/string.c M payloads/libpayload/bin/lpgcc M payloads/libpayload/drivers/storage/ahci_common.c M payloads/libpayload/drivers/usb/uhci.c M payloads/libpayload/include/x86/arch/exception.h M payloads/libpayload/libc/Makefile.mk M payloads/libpayload/vboot/Makefile.mk 18 files changed, 674 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81968/68 -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 68 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> [View Less]

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 21 May '24

21 May '24

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/81968?usp=email ) Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... Patch Set 67: (1 comment) File payloads/libpayload/arch/x86/pt.S: https://review.coreboot.org/c/coreboot/+/81968/comment/a49a70c9_24288725?us… : PS64, … [View More]

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[S] Change in coreboot[main]: [UNTESTED, WIP] device/pci_rom: handle non-remapped VGA_BIOS_ID
by Felix Held (Code Review) 21 May '24

21 May '24

Attention is currently required from: Matt DeVillier, Nico Huber. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82592?usp=email ) Change subject: [UNTESTED, WIP] device/pci_rom: handle non-remapped VGA_BIOS_ID ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: would be good to fix the underlying issue instead, but especially handing seabios the pci device to vbios image … [View More]

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[S] Change in coreboot[master]: device/pci_rom: rework PCI ID remapping in pci_rom_probe
by Felix Held (Code Review) 21 May '24

21 May '24

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/73612?usp=email ) Change subject: device/pci_rom: rework PCI ID remapping in pci_rom_probe ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > ouch, the x230 mainboard Kconfig is overriding the SoC default to a non-working value. […] pushed CB:82592 as an untested rfc to work around the issue until we have a proper fix -… [View More]

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coreboot-gerrit May 2024