coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: drivers/soundwire/alc711: Fix error in alc711 codec address field
by Anil Kumar K (Code Review) 30 Apr '24

30 Apr '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81952?usp=email to look at the new patch set (#3). Change subject: drivers/soundwire/alc711: Fix error in alc711 codec address field ...................................................................... drivers/soundwire/alc711: Fix error in alc711 codec address field Update Soundwire specification version to 1.2 and MIPI class to MIPI_CLASS_SDCA in alc711 codec soundwire address field. TEST=build coreboot image and boot on Intel RVP board. Disassemble SSDT and confirm ACPI entries are correct for alc711 device. Test audio playback and capture. Change-Id: I5ece9976ab174659ebd0ae95330ca3deb0481f2a Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> --- M src/drivers/soundwire/alc711/alc711.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81952/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ece9976ab174659ebd0ae95330ca3deb0481f2a Gerrit-Change-Number: 81952 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/soundwire/alc711: Fix error in alc711 codec address field
by Anil Kumar K (Code Review) 30 Apr '24

30 Apr '24

Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81952?usp=email ) Change subject: drivers/soundwire/alc711: Fix error in alc711 codec address field ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/81952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ece9976ab174659ebd0ae95330ca3deb0481f2a Gerrit-Change-Number: 81952 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 30 Apr 2024 20:41:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: spd.h: Move enum ddr5_module_type to ddr5.h
by Elyes Haouas (Code Review) 30 Apr '24

30 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82123?usp=email ) Change subject: spd.h: Move enum ddr5_module_type to ddr5.h ...................................................................... spd.h: Move enum ddr5_module_type to ddr5.h Move specific enum ddr5_module_type to <device/dram/ddr5.h>. Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/dram/spd.c M src/include/device/dram/ddr5.h M src/include/spd.h M tests/lib/dimm_info_util-test.c 4 files changed, 18 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/82123/1 diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index 4a1e882..c4ccfee 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -2,6 +2,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr5.h> #include <device/dram/spd.h> #include <spd.h> #include <stddef.h> diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index ff1604a..37182da 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -15,6 +15,22 @@ /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR5 1024 +enum ddr5_module_type { + DDR5_SPD_RDIMM = 0x01, + DDR5_SPD_UDIMM = 0x02, + DDR5_SPD_SODIMM = 0x03, + DDR5_SPD_LRDIMM = 0x04, + DDR5_SPD_MINI_RDIMM = 0x05, + DDR5_SPD_MINI_UDIMM = 0x06, + DDR5_SPD_72B_SO_UDIMM = 0x08, + DDR5_SPD_72B_SO_RDIMM = 0x09, + DDR5_SPD_SOLDERED_DOWN = 0x0b, + DDR5_SPD_16B_SO_DIMM = 0x0c, + DDR5_SPD_32B_SO_RDIMM = 0x0d, + DDR5_SPD_1DPC = 0x0e, + DDR5_SPD_2DPC = 0x0f, +}; + /** * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s */ diff --git a/src/include/spd.h b/src/include/spd.h index 2fe9f96..b456680 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -215,22 +215,6 @@ DDR4_SPD_32B_SO_RDIMM = 0x0d, }; -enum ddr5_module_type { - DDR5_SPD_RDIMM = 0x01, - DDR5_SPD_UDIMM = 0x02, - DDR5_SPD_SODIMM = 0x03, - DDR5_SPD_LRDIMM = 0x04, - DDR5_SPD_MINI_RDIMM = 0x05, - DDR5_SPD_MINI_UDIMM = 0x06, - DDR5_SPD_72B_SO_UDIMM = 0x08, - DDR5_SPD_72B_SO_RDIMM = 0x09, - DDR5_SPD_SOLDERED_DOWN = 0x0b, - DDR5_SPD_16B_SO_DIMM = 0x0c, - DDR5_SPD_32B_SO_RDIMM = 0x0d, - DDR5_SPD_1DPC = 0x0e, - DDR5_SPD_2DPC = 0x0f, -}; - enum lpx_module_type { LPX_SPD_LPDIMM = 0x07, LPX_SPD_NONDIMM = 0x0e, diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index 43fe6c9..3d11416 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -2,6 +2,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr5.h> #include <dimm_info_util.h> #include <spd.h> #include <tests/test.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/82123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d Gerrit-Change-Number: 82123 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Cliff Huang (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81333?usp=email ) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81333/comment/1649d57a_d66570ae : PS4, Line 13: minor Rework > Minor rework … Done https://review.coreboot.org/c/coreboot/+/81333/comment/d2f8247f_4cf5a693 : PS4, Line 9: GPIO pad configuration for THC1 according to CBI fw_config. : ACPI entries in SSDT for ELAN according to CBI fw_config. : : THC0 must be enabled when THC1 is enabled. : Major rework is required for Rex P1 and P2. minor Rework is needed for : EVT. Rex with THC rework won't be able to support UWB and FPCMU. : The touch device must be converted to SPI interface. : When THC is enabled and the THC rework is in place, the UWB and FPMCU : are not supported and need to be disable from the CBI. : THC0 will also be provided with ACPI entries when THC1 is enabled. : THC1 GPIO pins will be configured for THC according to the CBI : TOUCHSCREEN fw_config field. : The resistor on the THC-SPI MISO pin should be 100 Ohm. > ok. let me make changes. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 20:34:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: arch/io.h: Add port I/O functions to other architectures
by Julius Werner (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Alper Nebi Yasak, Arthur Heymans, Nico Huber, Shelley Chen, Yu-Ping Wu, ron minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80372?usp=email ) Change subject: arch/io.h: Add port I/O functions to other architectures ...................................................................... Patch Set 5: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/80372/comment/90ca6f44_118adbdf : PS5, Line 532: CPU communicate with peripheral devices over PCI I/O space. > There's definitely PCI hardware in the world that would need it. However, […] +Shelley, +Yu-Ping, do you know more details about how PCI I/O accesses work on Arm? Do the PCI devices we've used for now just not use any I/O space resources, or how did we solve this problem there? Sorry, I have to admit I know basically nothing about PCI and have no practical experience with those drivers. All I know is that from the point of view of an Arm CPU, there is no I/O bus and the concept of a global, peripheral-independent `inb()` function doesn't really make sense. However, if you say that it makes PCI programming and driver reuse easier in practice to treat it that way I might be swayed to see your point. The fact that Linux seems to do it this way as well is certainly a good argument. So if we do translate this by just adding `CONFIG_PCI_IOBASE` to everything, where does that IOBASE come from in the hardware? Is this hardwired in the SoC? Is it dynamically set up somehow? If so, where does the address space come from? (In my experience, Arm SoCs don't tend to have the kind of "memory holes" in the middle of their DRAM that x86 has — DRAM is contiguous in linear address space and everything else has its own hardwired offsets.) I mostly want to make sure that we can really have this thing in a Kconfig even if there are multiple PCI devices needing it or even multiple PCI controllers (is that a thing that happens in practice?) in the system. Is it really guaranteed to always just be a single global window that counts for everything? -- To view, visit https://review.coreboot.org/c/coreboot/+/80372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Gerrit-Change-Number: 80372 Gerrit-PatchSet: 5 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 20:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/rex: Add Intel Touch for controller 1 for Rex
by Cliff Huang (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jingyuan Liang, Kapil Porwal, Kyoung Il Kim, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81333?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex: Add Intel Touch for controller 1 for Rex ...................................................................... mb/google/rex: Add Intel Touch for controller 1 for Rex This patch enables THC1 support for Rex according to the corresponding CBI fw_config. The change includes the GPIO pad configuration and adding ACPI entries in SSDT for ELAN touch device. THC0 is also enabled when THC1 is enabled due to the design constraint. NOTE for Rework info: - Major rework is required when using THC1 with Rex P1 and P2. Minor rework is needed for EVT. - Rex with THC rework won't be able to support UWB and FPCMU as the original board does. And their CBI fw_config shouled be disabled to avoid conflict with THC1. - The resistor on the THC1 THC-SPI MISO pin should be 100 Ohm. NOTE for downstream device: - The ELAN touch device interface must be converted from I2C to SPI prior to use. BUG=b:307775082 TEST=set CBI TOUCHSREEN fw_config to TOUCHSCREEN_THC, FP fw_config to FP_ABSENT, and UWB fw_config to UWB_ABSENT. boot Rex to OS and run lspci to check THC device and check that THC device driver initialization successfully. /sys/class/hidraw/hidraw0/device/input/ should have several inputs enumerated. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/rex0/fw_config.c M src/mainboard/google/rex/variants/rex0/overridetree.cb 3 files changed, 163 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81333/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id89b5b46d67b90491410d3d08c1a3ae9549b4da5 Gerrit-Change-Number: 81333 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Jingyuan Liang <jingyliang(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: device/dram/ddr4: Use 'info->dimm_type'
by Elyes Haouas (Code Review) 30 Apr '24

30 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82122?usp=email ) Change subject: device/dram/ddr4: Use 'info->dimm_type' ...................................................................... device/dram/ddr4: Use 'info->dimm_type' Just use 'info->dimm_type' instead of using 'switch'. Change-Id: Ia538d2c73affa6560fa1533a40c02b3677588f5a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/dram/ddr4.c 1 file changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/82122/1 diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 37bd4e2..9a8c5eb 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -272,25 +272,7 @@ dimm->dimm_num = slot; memcpy(dimm->module_part_number, info->part_number, SPD_DDR4_PART_LEN); dimm->mod_id = info->manufacturer_id; - - switch (info->dimm_type) { - case SPD_DDR4_DIMM_TYPE_SO_DIMM: - dimm->mod_type = DDR4_SPD_SODIMM; - break; - case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = DDR4_SPD_72B_SO_RDIMM; - break; - case SPD_DDR4_DIMM_TYPE_UDIMM: - dimm->mod_type = DDR4_SPD_UDIMM; - break; - case SPD_DDR4_DIMM_TYPE_RDIMM: - dimm->mod_type = DDR4_SPD_RDIMM; - break; - default: - dimm->mod_type = SPD_UNDEFINED; - break; - } - + dimm->mod_type = info->dimm_type; dimm->bus_width = info->bus_width; memcpy(dimm->serial, info->serial_number, MIN(sizeof(dimm->serial), sizeof(info->serial_number))); -- To view, visit https://review.coreboot.org/c/coreboot/+/82122?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia538d2c73affa6560fa1533a40c02b3677588f5a Gerrit-Change-Number: 82122 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/phoenix/include/platform_descriptor: remove TODO
by Matt DeVillier (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82150?usp=email ) Change subject: soc/amd/phoenix/include/platform_descriptor: remove TODO ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9d7b5e8d8d6c8c22c2fae8e89d073481d21d8bdc Gerrit-Change-Number: 82150 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Apr 2024 20:08:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Release bmp_logo during READY_TO_BOOT stage
by Matt DeVillier (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Andrey Petrov, Karthik Ramasubramanian, Ronak Kanabar, Subrata Banik, Tim Van Patten. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82121?usp=email ) Change subject: drivers/intel/fsp2_0: Release bmp_logo during READY_TO_BOOT stage ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > can we do the bmp logo release as part of the finalize phase rather trying to bind it against fsp callbacks? SGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/82121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Gerrit-Change-Number: 82121 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 20:08:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUID
by CoolStar (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Felix Singer, Matt Delco, Paul Menzel, Sugnan Prabhu S. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82068?usp=email ) Change subject: drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUID ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82068/comment/f803341c_5102ad91 : PS1, Line 9: Tested on google/brya (kano) : > Thank you for the clarification. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6089f6bd841333882e28de9307fe5e48e368d02 Gerrit-Change-Number: 82068 Gerrit-PatchSet: 3 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Matt Delco <delco(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 19:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2024