coreboot-gerrit April 2024

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[L] Change in coreboot[main]: mb/dell: Add Latitude E5530 (Ivy Bridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82125?usp=email ) Change subject: mb/dell: Add Latitude E5530 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E5530 (Ivy Bridge) Mainboard is QXW10/LA-7902P (UMA). I do not physically have this system; it was ported based on autoport output sent to me which I then manually modified. This was originally tested and found to be working as a standalone board port in Libreboot, but this version in upstream coreboot that is set up as a variant has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb 7 files changed, 287 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82125/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index 0337727..183a67b 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -17,6 +17,11 @@ select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT +config BOARD_DELL_LATITUDE_E5530 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 + select SOUTHBRIDGE_INTEL_C216 + config BOARD_DELL_LATITUDE_E6430 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_12288 @@ -38,6 +43,7 @@ default "dell/snb_ivb_latitude" config MAINBOARD_PART_NUMBER + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 @@ -48,6 +54,7 @@ default 2 config VARIANT_DIR + default "e5530" if BOARD_DELL_LATITUDE_E5530 default "e6430" if BOARD_DELL_LATITUDE_E6430 default "e6530" if BOARD_DELL_LATITUDE_E6530 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index d89185d..c15ef40 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_DELL_LATITUDE_E5530 + bool "Latitude E5530" + config BOARD_DELL_LATITUDE_E6430 bool "Latitude E6430" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt new file mode 100644 index 0000000..3c54b70 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c new file mode 100644 index 0000000..00fd5f6 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 0, 3 }, + { 1, 2, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 }, + { 1, 1, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c new file mode 100644 index 0000000..0599f13 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c new file mode 100644 index 0000000..4c7c36e --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76df, /* Codec Vendor / Device ID: IDT */ + 0x1028053d, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1028053d), + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0x400000f0), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb new file mode 100644 index 0000000..502cd8f --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb @@ -0,0 +1,18 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_pch_backlight" = "0x03d003d0" + + device domain 0 on + subsystemid 0x1028 0x053d inherit + + chip southbridge/intel/bd82x6x + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end + device ref gbe off end + device ref pcie_rp7 on end # BCM5761 Ethernet + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Gerrit-Change-Number: 82125 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6430 (Ivy Bridge)
by Nicholas Chin (Code Review) 01 May '24

01 May '24

Attention is currently required from: Martin L Roth, Paul Menzel. Hello Martin L Roth, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77444?usp=email to look at the new patch set (#10). Change subject: mb/dell: Add Latitude E6430 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E6430 (Ivy Bridge) Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU model was not tested. This is based on the autoport output with some manual tweaks. The flash is 8MiB + 4MiB, and can be easily accessed by removing the keyboard. It can also be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Working: - Libgfxinit - USB EHCI debug (left side usb port is HCD index 2, middle port on the right side is HCD index 1) - Keyboard - Touchpad/trackpoint - ExpressCard - Audio - Ethernet - SD card reader - mPCIe WiFi - SeaBIOS 1.16.2 - edk2 (MrChromebox' fork, uefipayload_202306) - Internal flashing using dell-flash-unlock Not working: - S3 suspend: Possibly EC related, DRAM power is getting cut when entering S3 - Physical wireless switch - this triggers an SMI handler in the vendor firmware which sends commands to the EC to enable/disable wireless devices, and has not been reimplemented - Battery reporting - needs ACPI code for the EC - Brightness hotkeys - probably EC related Unknown/untested: - Dock - eSATA - TPM - dGPU on non-UMA model - Bluetooth module (not included on my system) [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/dell/snb_ivb_latitude/Kconfig A src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/Makefile.mk A src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl A src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl A src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl A src/mainboard/dell/snb_ivb_latitude/acpi_tables.c A src/mainboard/dell/snb_ivb_latitude/board_info.txt A src/mainboard/dell/snb_ivb_latitude/cmos.default A src/mainboard/dell/snb_ivb_latitude/cmos.layout A src/mainboard/dell/snb_ivb_latitude/devicetree.cb A src/mainboard/dell/snb_ivb_latitude/dsdt.asl A src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads A src/mainboard/dell/snb_ivb_latitude/mainboard.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb 19 files changed, 605 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/77444/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/77444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Gerrit-Change-Number: 77444 Gerrit-PatchSet: 10 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Iru Cai <mytbk920423(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Release bmp_logo during READY_TO_BOOT stage
by Karthik Ramasubramanian (Code Review) 01 May '24

01 May '24

Attention is currently required from: Andrey Petrov, Matt DeVillier, Ronak Kanabar, Subrata Banik, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82121?usp=email ) Change subject: drivers/intel/fsp2_0: Release bmp_logo during READY_TO_BOOT stage ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > what if any platform decide to not call into fsp notify phases like intel platform starting from adl? in that case, we won't be releasing the bmp logo? notify.c is enabled in ramstage for all platforms. FSP notify phase is skipped at run-time for ADL and MTL. Even there, bmp logo buffer is released since the release operation is done outside the fsp_notify. > can we do the bmp logo release as part of the finalize phase rather trying to bind it against fsp callbacks? Each SoC has soc_finalize callback in Intel platforms whereas AMD has a common soc_finalize callback. This scatters bmp_release_logo throughout the code-base and there are chances where we may forget to release it on certain SoCs. How about registering a callback in silicon_init.c that gets called during BS_PAYLOAD_LOAD as follows: ``` static void release_logo(void *arg_unused) { if (CONFIG(BMP_LOGO)) bmp_release_logo(); } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, release_logo, NULL); ``` This keeps it contained within FSP related code-base and easy to follow through in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/82121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Gerrit-Change-Number: 82121 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 23:28:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Clean up device enablement configuration
by Shuo Liu (Code Review) 01 May '24

01 May '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82120?usp=email ) Change subject: soc/intel/xeon_sp: Clean up device enablement configuration ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82120?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493 Gerrit-Change-Number: 82120 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 23:23:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: commonlib: Add skip_atoi()
by Julius Werner (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Maximilian Brune. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78026?usp=email ) Change subject: commonlib: Add skip_atoi() ...................................................................... Patch Set 3: (2 comments) Patchset: PS1: > Its been a while, but I guess that this is what you had in mind? When I said "move into commonlib" I meant commonlib/bsd, so that you can actually share it with libpayload (unless you want to hide this behind CONFIG_GPL... but for a small utility function like this that seems silly). Again, I'm not a lawyer but I would still recommend at least reimplementing this with new code to lower the chance of relicensing concerns, e.g. how about this: ``` unsigned int skip_atoi(char **ptr) { unsigned int result = 0; for (char *str = *ptr; isdigit(str[0]); str++) result = result * 10 + (str[0] - '0'); *ptr = str; } ``` File src/commonlib/string.c: https://review.coreboot.org/c/coreboot/+/78026/comment/cb4d7e71_e2321fe7 : PS3, Line 2: Needs to include `<ctype.h>` for `isdigit()`. (You could also move all of ctype into commonlib if you want. There's a libpayload version there so licensing shouldn't be an issue. Although I think making them static inlines like coreboot does makes more sense.) -- To view, visit https://review.coreboot.org/c/coreboot/+/78026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73cd36ff370e15d5b6242c3b07b14d1724f8ac24 Gerrit-Change-Number: 78026 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 21:54:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/crossgcc: Update GCC from 13.2 to 14.1.0-RC-20240430
by Felix Singer (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth. Hello Elyes Haouas, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81683?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/crossgcc: Update GCC from 13.2 to 14.1.0-RC-20240430 ...................................................................... util/crossgcc: Update GCC from 13.2 to 14.1.0-RC-20240430 Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-14.1.0-RC-20240430_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_gnat.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_libcpp.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_libgcc.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_rv32iafc.patch D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14.1.0-RC-20240430.tar.xz.cksum 9 files changed, 11 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81683/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Gerrit-Change-Number: 81683 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: util/crossgcc: Update LLVM from 17.0.6 to 18.1.4
by Felix Singer (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Arthur Heymans, Elyes Haouas, Felix Singer, Martin L Roth, Zebreus. Felix Singer has uploaded a new patch set (#16) to the change originally created by Zebreus. ( https://review.coreboot.org/c/coreboot/+/80314?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/crossgcc: Update LLVM from 17.0.6 to 18.1.4 ...................................................................... util/crossgcc: Update LLVM from 17.0.6 to 18.1.4 Change-Id: I03a44e0c23a925396f614f282882405dc886ba58 Signed-off-by: Lennart Eichhorn <lennarteichhorn(a)googlemail.com> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/libunwind-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/libunwind-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/lld-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/lld-18.1.4.src.tar.xz.cksum D util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-18.1.4.src.tar.xz.cksum 15 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/80314/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/80314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03a44e0c23a925396f614f282882405dc886ba58 Gerrit-Change-Number: 80314 Gerrit-PatchSet: 16 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: crossgcc: upgrade nasm from 2.16.01 to 2.16.03
by Felix Singer (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Singer, Jason Glenesk, Martin L Roth. Felix Singer has uploaded a new patch set (#5) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81900?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: crossgcc: upgrade nasm from 2.16.01 to 2.16.03 ...................................................................... crossgcc: upgrade nasm from 2.16.01 to 2.16.03 Change-Id: I70408b189b974f8abaadc66f0c809a1dbe10504b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch D util/crossgcc/sum/nasm-2.16.01.tar.bz2.cksum A util/crossgcc/sum/nasm-2.16.03.tar.bz2.cksum 4 files changed, 2 insertions(+), 233 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/81900/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70408b189b974f8abaadc66f0c809a1dbe10504b Gerrit-Change-Number: 81900 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: spd.h: Move enum ddr4_module_type to ddr4.h
by Elyes Haouas (Code Review) 30 Apr '24

30 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82124?usp=email ) Change subject: spd.h: Move enum ddr4_module_type to ddr4.h ...................................................................... spd.h: Move enum ddr4_module_type to ddr4.h Move specific enum ddr4_module_type to <device/dram/ddr4.h>. Change-Id: I33afccb768eaee94cc1cd947eb0ddbe15c2831bd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/device/dram/ddr3.c M src/device/dram/ddr4.c M src/device/dram/spd.c M src/include/device/dram/ddr3.h M src/include/device/dram/ddr4.h M src/include/spd.h M src/northbridge/intel/haswell/native_raminit/raminit_native.h M src/northbridge/intel/sandybridge/raminit.c M src/soc/intel/baytrail/romstage/raminit.c M tests/lib/dimm_info_util-test.c 10 files changed, 30 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/82124/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 1fa3f4c..8d2752b 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -97,7 +97,7 @@ * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd) +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd) { int ret; u16 crc, spd_crc; @@ -122,7 +122,7 @@ dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; dimm->dimm_type = spd[3] & 0xf; - crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data)); + crc = spd_ddr3_calc_crc(spd, sizeof(spd_ddr3_raw_data)); /* Compare with the CRC in the SPD */ spd_crc = (spd[127] << 8) + spd[126]; /* Verify the CRC is correct */ @@ -390,7 +390,7 @@ * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd, +int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile) { int ret; diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 9a8c5eb..6ccef72 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -70,7 +70,7 @@ {.type = BLOCK_3, 384, 128, 0} }; -static bool verify_block(const spd_block *block, spd_raw_data spd) +static bool verify_block(const spd_block *block, spd_ddr4_raw_data spd) { uint16_t crc, spd_crc; @@ -136,7 +136,7 @@ * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD * SPD_STATUS_CRC_ERROR -- checksum mismatch */ -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd) +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd) { u8 reg8; u8 bus_width, sdram_width; diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index c4ccfee..ae55ee5 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -2,6 +2,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> #include <device/dram/ddr5.h> #include <device/dram/spd.h> #include <spd.h> @@ -113,18 +114,18 @@ struct spd_info *info) { switch (module_type) { - case DDR4_SPD_RDIMM: - case DDR4_SPD_MINI_RDIMM: + case SPD_DDR4_DIMM_TYPE_RDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR4_SPD_UDIMM: - case DDR4_SPD_MINI_UDIMM: + case SPD_DDR4_DIMM_TYPE_UDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR4_SPD_SODIMM: - case DDR4_SPD_72B_SO_UDIMM: + case SPD_DDR4_DIMM_TYPE_SO_DIMM: + case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 6efe049..65977b4 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -153,15 +153,15 @@ DDR3_XMP_PROFILE_2 = 1, }; -typedef u8 spd_raw_data[256]; +typedef u8 spd_ddr3_raw_data[SPD_SIZE_MAX_DDR3]; u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd_data); int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type); void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, - spd_raw_data spd, + spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile); enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 7210212..da7359a 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -64,9 +64,9 @@ bool ecc_extension; }; -typedef u8 spd_raw_data[512]; +typedef u8 spd_ddr4_raw_data[SPD_SIZE_MAX_DDR4]; -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd); +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd); enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/spd.h b/src/include/spd.h index b456680..ff0cd64 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,20 +201,6 @@ #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 3 [3:0]: DDR4 Module type information */ -enum ddr4_module_type { - DDR4_SPD_RDIMM = 0x01, - DDR4_SPD_UDIMM = 0x02, - DDR4_SPD_SODIMM = 0x03, - DDR4_SPD_LRDIMM = 0x04, - DDR4_SPD_MINI_RDIMM = 0x05, - DDR4_SPD_MINI_UDIMM = 0x06, - DDR4_SPD_72B_SO_RDIMM = 0x08, - DDR4_SPD_72B_SO_UDIMM = 0x09, - DDR4_SPD_16B_SO_DIMM = 0x0c, - DDR4_SPD_32B_SO_RDIMM = 0x0d, -}; - enum lpx_module_type { LPX_SPD_LPDIMM = 0x07, LPX_SPD_NONDIMM = 0x0e, diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h index 1a07939..acb4c8b 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -33,7 +33,7 @@ }; struct raminit_dimm_info { - spd_raw_data raw_spd; + spd_drr3_raw_data raw_spd; struct dimm_attr_ddr3_st data; uint8_t spd_addr; bool valid; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2b59b9e..2a4eae5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -123,7 +123,7 @@ } /* Return CRC16 match for all SPDs */ -static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +static int verify_crc16_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) { int channel, slot, spd_slot; int match = 1; @@ -132,13 +132,13 @@ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; match &= ctrl->spd_crc[channel][slot] == - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data)); } } return match; } -static void read_spd(spd_raw_data *spd, u8 addr, bool id_only) +static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only) { int j; if (id_only) { @@ -150,7 +150,7 @@ } } -static void mainboard_get_spd(spd_raw_data *spd, bool id_only) +static void mainboard_get_spd(spd_ddr3_raw_data *spd, bool id_only) { const struct northbridge_intel_sandybridge_config *cfg = config_of_soc(); unsigned int i; @@ -192,7 +192,7 @@ } /* CONFIG(HAVE_SPD_IN_CBFS) */ } -static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +static void dram_find_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; int channel, slot, spd_slot; @@ -254,7 +254,7 @@ /* Fill in CRC16 for MRC cache */ ctrl->spd_crc[channel][slot] = - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data)); if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { /* Mark DIMM as invalid */ @@ -339,7 +339,7 @@ { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; - spd_raw_data spds[4]; + spd_ddr3_raw_data spds[4]; size_t mrc_size; ramctr_timing *ctrl_cached = NULL; diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index b64364b..6244072 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -59,7 +59,7 @@ enum spd_status status; /* Decode into dimm_attr struct */ - status = spd_decode_ddr3(&dimm, *(spd_raw_data *)dram_data); + status = spd_decode_ddr3(&dimm, *(spd_ddr3_raw_data *)dram_data); /* Some SPDs have bad CRCs, nothing we can do about it */ if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) { diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index 3d11416..c83093b 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -2,6 +2,7 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> #include <device/dram/ddr5.h> #include <dimm_info_util.h> #include <spd.h> @@ -157,9 +158,9 @@ }, { .memory_type = MEMORY_TYPE_DDR4, - .udimm_allowed = {DDR4_SPD_UDIMM, DDR4_SPD_MINI_UDIMM}, - .rdimm_allowed = {DDR4_SPD_RDIMM, DDR4_SPD_MINI_RDIMM}, - .expected_module_type = DDR4_SPD_SODIMM, + .udimm_allowed = {SPD_DDR4_DIMM_TYPE_UDIMM, SPD_DDR4_DIMM_TYPE_MINI_UDIMM}, + .rdimm_allowed = {SPD_DDR4_DIMM_TYPE_RDIMM, SPD_DDR4_DIMM_TYPE_MINI_RDIMM}, + .expected_module_type = SPD_DDR4_DIMM_TYPE_SO_DIMM, }, {.memory_type = MEMORY_TYPE_DDR5, .udimm_allowed = {DDR5_SPD_UDIMM, DDR5_SPD_MINI_UDIMM}, -- To view, visit https://review.coreboot.org/c/coreboot/+/82124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33afccb768eaee94cc1cd947eb0ddbe15c2831bd Gerrit-Change-Number: 82124 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Makefile.mk: Align romstage to page directory pointer requirements
by Julius Werner (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Appukuttan V K, Arthur Heymans, Dinesh Gehlot, Lean Sheng Tan, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82102?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Makefile.mk: Align romstage to page directory pointer requirements ...................................................................... Patch Set 2: (1 comment) File Makefile.mk: https://review.coreboot.org/c/coreboot/+/82102/comment/d61386f8_79ee4b9a : PS1, Line 1282: In the : # future cbfstool should add XIP files proper and honor the alignment : # requirements of the program segment. Should we consider trying to do this instead of always fixing up this hardcoded value? cbfstool does run `convert()` before `locate()` nowadays (which I think might not have been the case when this was written), so it should be possible to decide the alignment in the XIP parsing step (based on the highest `phdr->p_align`). -- To view, visit https://review.coreboot.org/c/coreboot/+/82102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8 Gerrit-Change-Number: 82102 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 21:03:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2024