April 2024 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: mb/yanling: Add Yanling YL-KBR6L mainboard + doc
by Thomas (Code Review) June 8, 2024

June 8, 2024

Thomas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48769 ) Change subject: mb/yanling: Add Yanling YL-KBR6L mainboard + doc ...................................................................... mb/yanling: Add Yanling YL-KBR6L mainboard + doc The Yanling YL-KBR6L (aka Yanling N18) is a Protecli FW6 with a newer CPUs (i5-8250U), different SuperIO chip (ITE IT8613F), slightly different (newer?) flash memory chip (MX25L6436F) and support for a mPCIe modem. Working: - USB 3.0 front ports (SeaBIOS, Linux and FreeBSD) - 6 Ethernet ports - HDMI port with libgfxinit and VGA Option ROM - flashrom - PCIe WiFi - SATA and mSATA - mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe) - Super I/O serial port 0 (RS232 via front RJ45 connector) - SeaBIOS payload (version rel-1.14.0) - Booting Ubuntu 20.04, FreeBSD 12.2 - 64GB RAM (tested with Crucial CT2K32G4SFD8266) Untested (same as Protectli FW6): - Internal USB 2.0 headers - Boot with cleaned ME Misc: - Removed "ProbelessTrace" in devicetree as done for other boards by coreboot. Change-Id: Icbc18914670f87f0943b371400c509ff0eeacf6a Signed-off-by: Thomas Kupper <thomas.kupper(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/yanling/yl-kbr6l.md A Documentation/mainboard/yanling/yl-kbr6l_front.jpg A src/mainboard/yanling/Kconfig A src/mainboard/yanling/Kconfig.name A src/mainboard/yanling/yl_kbr6l/Kconfig A src/mainboard/yanling/yl_kbr6l/Kconfig.name A src/mainboard/yanling/yl_kbr6l/Makefile.inc A src/mainboard/yanling/yl_kbr6l/acpi/ec.asl A src/mainboard/yanling/yl_kbr6l/acpi/superio.asl A src/mainboard/yanling/yl_kbr6l/board_info.txt A src/mainboard/yanling/yl_kbr6l/bootblock.c A src/mainboard/yanling/yl_kbr6l/data.vbt A src/mainboard/yanling/yl_kbr6l/devicetree.cb A src/mainboard/yanling/yl_kbr6l/dsdt.asl A src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads A src/mainboard/yanling/yl_kbr6l/gpio.h A src/mainboard/yanling/yl_kbr6l/ramstage.c A src/mainboard/yanling/yl_kbr6l/romstage.c 19 files changed, 820 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48769/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 95efe55..2480069 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -179,3 +179,7 @@ ## UP - [Squared](up/squared/index.md) + +## Yanling + +- [YL-KBR6L](yanling/yl-kbr6l.md) \ No newline at end of file diff --git a/Documentation/mainboard/yanling/yl-kbr6l.md b/Documentation/mainboard/yanling/yl-kbr6l.md new file mode 100644 index 0000000..28d1d56 --- /dev/null +++ b/Documentation/mainboard/yanling/yl-kbr6l.md @@ -0,0 +1,133 @@ +# Yanling YL-KBR6L + +This board and therefore its documentation is very, very similar to the Protectli FW6. This document is based on theirs, all praise to 3mdeb/Protectli. + +This page describes how to run coreboot on the [Yanling YL-KBR6L], or [Yanling N18] as it seems to be called officially (and its three CPU variants). + +![](yl-kbr6l_front.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Kaby Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by build +system from the `3rdparty/intel-microcode` submodule. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using libgfxinit). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first version +supporting the chipset is flashrom v1.1. Firmware an be easily flashed +with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. +This chip is located on the bottom side of the case (the radiator side). One +has to remove all screws (in order): 4 top cover screws, 4 side cover screws +(one side is enough), 4 mainboard screws, 4 CPU screws (under DIMMs). Lift up +the mainboard and turn around it. The flash chip is near the SoC on the DIMM +slots side. Use a clip (or solder the wires) to program the chip. Specifically, +it's a Macronix MX25L6436F M2I-08Q (3V) - [datasheet][MX25L6436F]. + +## Known issues + +- assume the same as for Protectli FW6: + +- After flashing with external programmer it is always required to reset RTC + with jumper or disconnect coin cell temporarily. Only then the platform will + boot after flashing. +- FW6A does not always work reliably with all DIMMs. Linux happens to hang or + gives many panics. This issue was present also with vendor BIOS. +- Sometimes FSPMemoryInit return errors or hangs (especially with 2 DIMMs + connected). A workaround is to power cycle the board (even a few times) or + temporarily disconnect DIMM when platform is powered off. +- When using libgfxinit and SeaBIOS bootsplash, the red color is dim + +## Untested + +- assume the same as for Protectli FW6: + +Not all mainboard's peripherals and functions were tested because of lack of +the cables or not being populated on the board case. + +- Internal USB 2.0 headers +- Boot with cleaned ME + +## Working + +- USB 3.0 front ports (SeaBIOS and Linux) +- 6 Ethernet ports +- HDMI port with libgfxinit and VGA Option ROM +- flashrom +- PCIe WiFi +- SATA and mSATA +- mPCIe Modem in mSATA slot (tested with Simcom SIM7100E mPCIe) +- Super I/O serial port 0 (RS232 via front RJ45 connector) +- SeaBIOS payload (version rel-1.14) +- Booting Ubuntu 20.04, FreeBSD 12.2 +- 64GB RAM (tested with Crucial CT2K32G4SFD8266) + +## Technology + +```eval_rst ++---------------------+-----------------------------------------------+ +| CPU | [Intel Core i5-8250U] | ++---------------------+-----------------------------------------------+ +| PCH | Kaby Lake U w/ iHDCP2.2 Premium | ++---------------------+-----------------------------------------------+ +| Super I/O, EC | ITE IT8613F | ++---------------------+-----------------------------------------------+ +| Coprocessor | Intel Management Engine | ++---------------------+-----------------------------------------------+ +| Ethernet Controller | 6x Intel I211AT | ++---------------------+-----------------------------------------------+ +``` +Information about the PCH can be found in [Intel 7th and 8th gen datasheet vol 1] and [Intel 7th and 8th gen datasheet vol 2]. + +## Ports + +```eval_rst ++---------------------+-----------------------------------------------+ +| Ethernet | 6x 1GbE | ++---------------------+-----------------------------------------------+ +| USB | 4x USB 3.0 | ++---------------------+-----------------------------------------------+ +| Serial/COM | 1x RJ-45 serial port | ++---------------------+-----------------------------------------------+ +| SATA | 1x mSATA (port 0) + 1x SATA 3.0 (port 1) | ++---------------------+-----------------------------------------------+ +| Cellular Modem | 1x mPCIe, shared with mSATA slot, nano-SIM | ++---------------------+-----------------------------------------------+ +| Wifi/Bluetooth | 1x mPCIe slot, under mSATA/Modem, | +| | supports half-size cards only | ++---------------------+-----------------------------------------------+ +``` + +[flashrom]: https://flashrom.org/Flashrom +[Intel 7th and 8th gen datasheet vol 1]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th… +[Intel 7th and 8th gen datasheet vol 2]: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/7th… +[MX25L6436F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7405/MX25L6436F,%203V,%… +[Yanling YL-KBR6L]: https://www.aliexpress.com/item/1005001813291053.html +[Yanling N18]:https://www.ylipc.com/product/network_server_network_server/N18_Firewa… diff --git a/Documentation/mainboard/yanling/yl-kbr6l_front.jpg b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Documentation/mainboard/yanling/yl-kbr6l_front.jpg diff --git a/src/mainboard/yanling/Kconfig b/src/mainboard/yanling/Kconfig new file mode 100644 index 0000000..2972a38 --- /dev/null +++ b/src/mainboard/yanling/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_YANLING + +choice + prompt "Mainboard model" + +source "src/mainboard/yanling/*/Kconfig.name" + +endchoice + +source "src/mainboard/yanling/*/Kconfig" + +config MAINBOARD_VENDOR + default "Yanling" + +endif # VENDOR_YANLING diff --git a/src/mainboard/yanling/Kconfig.name b/src/mainboard/yanling/Kconfig.name new file mode 100644 index 0000000..6cc7ef1 --- /dev/null +++ b/src/mainboard/yanling/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_YANLING + bool "Yanling" diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig b/src/mainboard/yanling/yl_kbr6l/Kconfig new file mode 100644 index 0000000..838bc44 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Kconfig @@ -0,0 +1,57 @@ +if BOARD_YANLING_YLKBR6L + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select SOC_INTEL_KABYLAKE + select SPI_FLASH_MACRONIX + select SUPERIO_ITE_IT8613E + select MAINBOARD_HAS_CRB_TPM + select HAVE_INTEL_PTT + select TPM2 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "yanling/yl_kbr6l" + +config MAINBOARD_PART_NUMBER + string + default "YLKBR6L" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,5917" + +config PXE_ROM_ID + string + default "8086,1539" + +config CBFS_SIZE + hex + default 0x600000 + +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/yanling/yl_kbr6l/Kconfig.name b/src/mainboard/yanling/yl_kbr6l/Kconfig.name new file mode 100644 index 0000000..8b039de --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_YANLING_YLKBR6L + bool "YLKBR6L" diff --git a/src/mainboard/yanling/yl_kbr6l/Makefile.inc b/src/mainboard/yanling/yl_kbr6l/Makefile.inc new file mode 100644 index 0000000..4cd7aac --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/acpi/ec.asl diff --git a/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/acpi/superio.asl diff --git a/src/mainboard/yanling/yl_kbr6l/board_info.txt b/src/mainboard/yanling/yl_kbr6l/board_info.txt new file mode 100644 index 0000000..c12e388 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Yanling +Board name: YL-KBR6L +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/yanling/yl_kbr6l/bootblock.c b/src/mainboard/yanling/yl_kbr6l/bootblock.c new file mode 100644 index 0000000..e35a7cc --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/ite/it8613e/it8613e.h> +#include <superio/ite/common/ite.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/yanling/yl_kbr6l/data.vbt b/src/mainboard/yanling/yl_kbr6l/data.vbt new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/data.vbt diff --git a/src/mainboard/yanling/yl_kbr6l/devicetree.cb b/src/mainboard/yanling/yl_kbr6l/devicetree.cb new file mode 100644 index 0000000..b57ab96 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/devicetree.cb @@ -0,0 +1,278 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "s0ix_enable" = "1" + + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + register "eist_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # Enable VT-d + register "ignore_vtd" = "0" + + # Enable SERIRQ continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "tcc_offset" = "5" # TCC of 95C + + # FSP Configuration + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "SsicPortEnable" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "SkipExtGfxScan" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "SaGv_Enabled" + register "IslVrCmd" = "2" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "4" # 4s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable SATA ports 1,2 + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + + # Enable Root ports. 1-6 for LAN and Root Port 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" # mPCIe WiFi + + # Enable Advanced Error Reporting for RP 1-6, 9 + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + + # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # TODO: Check why protectli used them and WiFi won't work + # for me if I set them -> err: lost pci device + # Enable RP 9 CLKREQ# support + #register "PcieRpClkReqSupport[8]" = "1" + # RP 9 uses CLKREQ0# + #register "PcieRpClkReqNumber[8]" = "0" + + # Clocks 0-5 for RP 1-6 + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpClkSrcNumber[1]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + register "PcieRpClkSrcNumber[3]" = "3" + register "PcieRpClkSrcNumber[4]" = "4" + register "PcieRpClkSrcNumber[5]" = "5" + # RP 9 shares CLKSRC5# with RP 6 + register "PcieRpClkSrcNumber[8]" = "5" + + + # USB 2.0 enable ports 1-8, disable ports 9-12 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot + + # USB 3.0 enable ports 1-4, disable ports 5-6 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Lock Down CHIPSET_LOCKDOWN_COREBOOT + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 5914 - Host Bridge + device pci 02.0 on end # 8086 5917 - Integrated Graphics Device + device pci 04.0 off end # 8086 ???? - SA thermal subsystem + device pci 05.0 off end # 8086 ???? - SA IMGU + device pci 08.0 off end # 8086 ???? - Gaussian Mixture Model + device pci 13.0 off end # 8086 9d35 - Integrated Sensor Hub + device pci 14.0 on end # 8086 9d2f - USB xHCI + device pci 14.1 off end # 8086 9d30 - USB xDCI (OTG) + device pci 14.2 off end # 8086 9d31 - Thermal Subsystem + device pci 14.3 off end # 8086 9d32 - Camera I/O Host Controller + device pci 15.0 off end # 8086 9d60 - I2C #0 + device pci 15.1 off end # 8086 9d61 - I2C #1 + device pci 15.2 off end # 8086 9d62 - I2C #2 + device pci 15.3 off end # 8086 9d63 - I2C #3 + device pci 16.0 on end # 8086 9d3a - Management Engine Interface 1 + device pci 16.1 off end # 8086 9d3b - Management Engine Interface 2 + device pci 16.2 off end # 8086 9d3c - Management Engine IDE-Redirection + device pci 16.3 off end # 8086 9d3d - Management Engine KT Redirection + device pci 16.4 off end # 8086 9d3e - Management Engine Interface 3 + device pci 17.0 on end # 8086 9d03 - SATA + device pci 19.0 off end # 8086 9d66 - UART #2 + device pci 19.1 off end # 8086 9d65 - I2C #5 + device pci 19.2 off end # 8086 9d64 - I2C #4 + device pci 1c.0 on end # 8086 9d10 - PCI Express Port 1 + device pci 1c.1 on end # 8086 9d11 - PCI Express Port 2 + device pci 1c.2 on end # 8086 9d12 - PCI Express Port 3 + device pci 1c.3 on end # 8086 9d13 - PCI Express Port 4 + device pci 1c.4 on end # 8086 9d14 - PCI Express Port 5 + device pci 1c.5 on end # 8086 9d15 - PCI Express Port 6 + device pci 1c.6 off end # 8086 9d16 - PCI Express Port 7 + device pci 1c.7 off end # 8086 9d17 - PCI Express Port 8 + device pci 1d.0 on # 8086 9d18 - PCI Express Port 9 - WiFi + smbios_slot_desc + "SlotTypePciExpressMini52pinWithoutBSKO" + "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" + end + device pci 1d.1 off end # 8086 9d19 - PCI Express Port 10 + device pci 1d.2 off end # 8086 9d1a - PCI Express Port 11 + device pci 1d.3 off end # 8086 9d1b - PCI Express Port 12 + device pci 1e.0 off end # 8086 9d27 - UART #0 + device pci 1e.1 off end # 8086 9d28 - UART #1 + device pci 1e.2 off end # 8086 9d29 - GSPI #0 + device pci 1e.3 off end # 8086 9d2a - GSPI #1 + device pci 1e.4 off end # 8086 9d2b - eMMC + device pci 1e.5 off end # 8086 ???? - SDIO + device pci 1e.6 off end # 8086 9d2d = SDXC + device pci 1f.0 on # 8086 9d4e - LPC Controller + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end # LPC Interface + device pci 1f.1 on end # 8086 9d20 - P2SB + device pci 1f.2 on end # 8086 9d21 - Power Management Controller + device pci 1f.3 off end # 8086 9d71 - Intel HDA + device pci 1f.4 on end # 8086 9d23 - SMBus + device pci 1f.5 off end # 8086 9d24 - PCH SPI + device pci 1f.6 off end # 8086 9d25 - GbE + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/yanling/yl_kbr6l/dsdt.asl b/src/mainboard/yanling/yl_kbr6l/dsdt.asl new file mode 100644 index 0000000..3de4e26 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads new file mode 100644 index 0000000..0e0f4f8 --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/gma-mainboard.ads @@ -0,0 +1,15 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/yanling/yl_kbr6l/gpio.h b/src/mainboard/yanling/yl_kbr6l/gpio.h new file mode 100644 index 0000000..7ec5a8a --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/gpio.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _GPIOFW6B_H +#define _GPIOFW6B_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA_N*/ PAD_CFG_TERM_GPO(GPP_A7, 1, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_LPC_CLK0 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), +/* PCH_LPC_CLK1 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), +/* PME# */ PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), +/* ISH_GP6 */ PAD_NC(GPP_A12, NONE), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSSTAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT_N */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0_N */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1_N*/ PAD_NC(GPP_B6, NONE), +/* SRCCLKREQ2_N*/ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3_N*/ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4_N*/ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5_N*/ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE_N */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), +/* GSPI0_CS_N */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS_N */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), +/* SML0_CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_CTS_N */ PAD_NC(GPP_C10, NONE), +/* UART0_RTS_N */ PAD_NC(GPP_C11, NONE), +/* UART1_RXD */ PAD_NC(GPP_C12, NONE), +/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_CTS_N */ PAD_NC(GPP_C14, NONE), +/* UART1_RTS_N */ PAD_NC(GPP_C15, NONE), +/* I2C0_SDA */ PAD_NC(GPP_C16, NONE), +/* I2C0_SCL */ PAD_NC(GPP_C17, NONE), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), +/* UART2_CTS_N */ PAD_NC(GPP_C22, NONE), +/* UART2_RTS_N */ PAD_NC(GPP_C23, NONE), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* FLASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* GPP_D9 */ PAD_NC(GPP_D9, NONE), +/* GPP_D10 */ PAD_NC(GPP_D10, NONE), +/* GPP_D11 */ PAD_NC(GPP_D11, NONE), +/* GPP_D12 */ PAD_NC(GPP_D12, NONE), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK_0 */ PAD_NC(GPP_D19, NONE), +/* DMIC_DATA_0 */ PAD_NC(GPP_D20, NONE), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), +/* I2S_MCLK */ PAD_NC(GPP_D23, NONE), +/* SATAXPCIE0 (TP8) */ PAD_NC(GPP_E0, NONE), +/* SATAXPCIE1 (TP9)*/ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 (TP10) */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATA_LED */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_NC(GPP_E9, NONE), +/* USB2_OC_1 */ PAD_NC(GPP_E10, NONE), +/* USB2_OC_2 */ PAD_NC(GPP_E11, NONE), +/* USB2_OC_3 */ PAD_NC(GPP_E12, NONE), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_NC(GPP_E14, NONE), +/* DDI3_HPD */ PAD_NC(GPP_E15, NONE), +/* DDI4_HPD */ PAD_NC(GPP_E16, NONE), +/* EDP_HPD */ PAD_NC(GPP_E17, NONE), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F9, NONE), +/* I2C5_SDA */ PAD_NC(GPP_F10, NONE), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* GPP_F23 */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), +/* PCH_BATLOW */ PAD_NC(GPD0, NONE), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE_N */ PAD_NC(GPD2, NONE), +/* PWRBTN */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# (TP7) */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7_RSVD */ PAD_CFG_TERM_GPO(GPD7, 1, NONE, DEEP), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# (TP6) */ PAD_NC(GPD9, NONE), +/* SLP_S5# (TP3) */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), +}; + +#endif + +#endif diff --git a/src/mainboard/yanling/yl_kbr6l/ramstage.c b/src/mainboard/yanling/yl_kbr6l/ramstage.c new file mode 100644 index 0000000..9518b1d --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> + +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* + * Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. + */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->TurboMode = 1; + params->PchPort61hEnable = 1; + params->CdClock = 3; +} diff --git a/src/mainboard/yanling/yl_kbr6l/romstage.c b/src/mainboard/yanling/yl_kbr6l/romstage.c new file mode 100644 index 0000000..2b68e1a --- /dev/null +++ b/src/mainboard/yanling/yl_kbr6l/romstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) +{ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) +{ + const u8 dqs_map[2][8] = { + { 0, 1, 2, 3, 4, 5, 6, 7 }, + { 1, 0, 2, 3, 4, 5, 6, 7 } }; + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + static const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbc18914670f87f0943b371400c509ff0eeacf6a Gerrit-Change-Number: 48769 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/braswell: Increase dcache size
by Shelley Chen (Code Review) May 8, 2024

May 8, 2024

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45827 ) Change subject: soc/intel/braswell: Increase dcache size ...................................................................... soc/intel/braswell: Increase dcache size Need to increase the DRAM cache size for braswell as the was getting the compilation error "Cache as RAM area is too full" when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5c9988c..077b5a1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -96,7 +96,7 @@ config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x5000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE -- To view, visit https://review.coreboot.org/c/coreboot/+/45827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Gerrit-Change-Number: 45827 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: [WIP] mb/hp: Add HP ProBook 640 G1
by Iru Cai (vimacs) (Code Review) May 2, 2024

May 2, 2024

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46130 to review the following change. Change subject: [WIP] mb/hp: Add HP ProBook 640 G1 ...................................................................... [WIP] mb/hp: Add HP ProBook 640 G1 Generate code from autoport. It boots to Arch Linux in a USB disk from SeaBIOS payload. EC ACPI doesn't work yet. This board doesn't have HP Sure Start enabled, so we can use all the flash regions, and relocate the EC firmware with CB:41393. Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/640g1.md A src/mainboard/hp/probook_640_g1/Kconfig A src/mainboard/hp/probook_640_g1/Kconfig.name A src/mainboard/hp/probook_640_g1/Makefile.inc A src/mainboard/hp/probook_640_g1/acpi/ec.asl A src/mainboard/hp/probook_640_g1/acpi/platform.asl A src/mainboard/hp/probook_640_g1/acpi/superio.asl A src/mainboard/hp/probook_640_g1/acpi_tables.c A src/mainboard/hp/probook_640_g1/board_info.txt A src/mainboard/hp/probook_640_g1/bootblock.c A src/mainboard/hp/probook_640_g1/devicetree.cb A src/mainboard/hp/probook_640_g1/dsdt.asl A src/mainboard/hp/probook_640_g1/gma-mainboard.ads A src/mainboard/hp/probook_640_g1/gpio.c A src/mainboard/hp/probook_640_g1/hda_verb.c A src/mainboard/hp/probook_640_g1/mainboard.c A src/mainboard/hp/probook_640_g1/romstage.c 17 files changed, 635 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46130/1 diff --git a/Documentation/mainboard/hp/640g1.md b/Documentation/mainboard/hp/640g1.md new file mode 100644 index 0000000..048633f --- /dev/null +++ b/Documentation/mainboard/hp/640g1.md @@ -0,0 +1,65 @@ +# HP ProBook 640 G1 + +This page is about the notebook [HP ProBook 640 G1]. + +## Release status + +(TBD) + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. mrc.bin + +HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. +The EC firmware is stored in the flash chip. We can extract the EC firmware from +the OEM firmware, and insert it in the coreboot image. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Haswell memory reference code binary is needed when building coreboot. +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Programming + +(TBD) + +## Debugging + +The serial port on dock can be used to debug the laptop. + +## Test status + +### Known issues + +(TBD) + +- EC ACPI is not working yet. + +### Untested + +(TBD) + +### Working + +(TBD) + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell (FCPGA946) | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point HM87 | ++------------------+-----------------------------+ +| EC | SMSC MEC1322 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP ProBook 640 G1]: https://support.hp.com/us-en/product/hp-probook-640-g1-notebook-pc/5405392/ +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04823617 diff --git a/src/mainboard/hp/probook_640_g1/Kconfig b/src/mainboard/hp/probook_640_g1/Kconfig new file mode 100644 index 0000000..d23a3fb --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Kconfig @@ -0,0 +1,42 @@ +if BOARD_HP_PROBOOK_640_G1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_SMSC_LPC47N217 + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/probook_640_g1" + +config MAINBOARD_PART_NUMBER + string + default "HP ProBook 640 G1" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +endif diff --git a/src/mainboard/hp/probook_640_g1/Kconfig.name b/src/mainboard/hp/probook_640_g1/Kconfig.name new file mode 100644 index 0000000..f809069 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_PROBOOK_640_G1 + bool "ProBook 640 G1" diff --git a/src/mainboard/hp/probook_640_g1/Makefile.inc b/src/mainboard/hp/probook_640_g1/Makefile.inc new file mode 100644 index 0000000..fa23791 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/probook_640_g1/acpi/ec.asl b/src/mainboard/hp/probook_640_g1/acpi/ec.asl new file mode 100644 index 0000000..ab3a35c --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/acpi/ec.asl> \ No newline at end of file diff --git a/src/mainboard/hp/probook_640_g1/acpi/platform.asl b/src/mainboard/hp/probook_640_g1/acpi/platform.asl new file mode 100644 index 0000000..8023ae8 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/probook_640_g1/acpi/superio.asl b/src/mainboard/hp/probook_640_g1/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/probook_640_g1/acpi_tables.c b/src/mainboard/hp/probook_640_g1/acpi_tables.c new file mode 100644 index 0000000..f9ac854 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/acpi_tables.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/probook_640_g1/board_info.txt b/src/mainboard/hp/probook_640_g1/board_info.txt new file mode 100644 index 0000000..28b9c2f --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +FIXME: put ROM package, ROM socketed, Release year +Board URL: https://support.hp.com/us-en/product/hp-probook-640-g1-notebook-pc/5405392/ diff --git a/src/mainboard/hp/probook_640_g1/bootblock.c b/src/mainboard/hp/probook_640_g1/bootblock.c new file mode 100644 index 0000000..b5b6d43 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/smsc/lpc47n217/lpc47n217.h> +#include <ec/hp/kbc1126/ec.h> + +#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1) + +void mainboard_config_superio(void) +{ + lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/probook_640_g1/devicetree.cb b/src/mainboard/hp/probook_640_g1/devicetree.cb new file mode 100644 index 0000000..4056b9d --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/devicetree.cb @@ -0,0 +1,88 @@ +chip northbridge/intel/haswell # FIXME: check ec_present, dq_pins_interleaved, usb_xhci_on_resume, gfx + register "dq_pins_interleaved" = "false" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "usb_xhci_on_resume" = "false" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x1993 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "sata_ahci" = "1" + register "sata_port0_gen3_dtle" = "0x7" + # 0(HDD), 1(ODD), 5(M.2) + register "sata_port_map" = "0x37" + device pci 14.0 on end # xHCI Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WLAN + device pci 1c.7 on end # PCIe Port #8, Card Reader + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x5f" + device pnp ff.1 off end + end + chip superio/smsc/lpc47n217 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/probook_640_g1/dsdt.asl b/src/mainboard/hp/probook_640_g1/dsdt.asl new file mode 100644 index 0000000..769d907 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/probook_640_g1/gma-mainboard.ads b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads new file mode 100644 index 0000000..a6af0ac --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/probook_640_g1/gpio.c b/src/mainboard/hp/probook_640_g1/gpio.c new file mode 100644 index 0000000..629117a --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/gpio.c @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio2 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio19 = GPIO_INVERT, + .gpio21 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/probook_640_g1/hda_verb.c b/src/mainboard/hp/probook_640_g1/hda_verb.c new file mode 100644 index 0000000..5c0f943 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x00000000, /* Codec Vendor / Device ID: */ + 0x00000000, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x00000000), + AZALIA_PIN_CFG(0, 0x0a, 0x21011030), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x0f, 0x2181102e), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30140), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/probook_640_g1/mainboard.c b/src/mainboard/hp/probook_640_g1/mainboard.c new file mode 100644 index 0000000..3f023d0 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/probook_640_g1/romstage.c b/src/mainboard/hp/probook_640_g1/romstage.c new file mode 100644 index 0000000..63c2fb8 --- /dev/null +++ b/src/mainboard/hp/probook_640_g1/romstage.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa2; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, /* dock */ + { 0x0080, 1, 0, USB_PORT_BACK_PANEL }, /* right */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* right */ + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* left */ + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0080, 1, 3, USB_PORT_DOCK }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* left */ + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* M.2 */ + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, /* WLAN */ + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 6, USB_PORT_DOCK }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 0, 2 }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07f433784292e3765bde3736414ff0eae525a046 Gerrit-Change-Number: 46130 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 13

[L] Change in coreboot[main]: mb/dell: Add Latitude E6230 (Ivy Bridge)
by Nicholas Chin (Code Review) April 30, 2024

April 30, 2024

Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82153?usp=email ) Change subject: mb/dell: Add Latitude E6230 (Ivy Bridge) ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Missing vbt -- To view, visit https://review.coreboot.org/c/coreboot/+/82153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369 Gerrit-Change-Number: 82153 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 23:55:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6220 (Sandy Bridge)
by Nicholas Chin (Code Review) April 30, 2024

April 30, 2024

Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82131?usp=email ) Change subject: mb/dell: Add Latitude E6220 (Sandy Bridge) ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Missing vbt -- To view, visit https://review.coreboot.org/c/coreboot/+/82131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c Gerrit-Change-Number: 82131 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 23:55:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6530 (Ivy Bridge)
by Nicholas Chin (Code Review) April 30, 2024

April 30, 2024

Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79012?usp=email ) Change subject: mb/dell: Add Latitude E6530 (Ivy Bridge) ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71 Gerrit-Change-Number: 79012 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Apr 2024 23:42:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6230 (Ivy Bridge)
by Nicholas Chin (Code Review) April 30, 2024

April 30, 2024

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82153?usp=email ) Change subject: mb/dell: Add Latitude E6230 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E6230 (Ivy Bridge) This was adapted from CB:22693 from Iru Cai, which was based on autoport. This new version has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Original-Change-Id: I8cdc01e902e670310628809416290045c2102340 Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb 6 files changed, 284 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82153/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index 49bf225..f6e0979 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -56,6 +56,12 @@ select BOARD_ROMSIZE_KB_12288 select SOUTHBRIDGE_INTEL_C216 +config BOARD_DELL_LATITUDE_E6230 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_C216 + config BOARD_DELL_LATITUDE_E6330 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_12288 @@ -90,6 +96,7 @@ default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 + default "Latitude E6230" if BOARD_DELL_LATITUDE_E6230 default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330 default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 @@ -108,6 +115,7 @@ default "e6420" if BOARD_DELL_LATITUDE_E6420 default "e6520" if BOARD_DELL_LATITUDE_E6520 default "e5530" if BOARD_DELL_LATITUDE_E5530 + default "e6230" if BOARD_DELL_LATITUDE_E6230 default "e6330" if BOARD_DELL_LATITUDE_E6330 default "e6430" if BOARD_DELL_LATITUDE_E6430 default "e6530" if BOARD_DELL_LATITUDE_E6530 @@ -121,7 +129,8 @@ || BOARD_DELL_LATITUDE_E5520 \ || BOARD_DELL_LATITUDE_E6220 \ || BOARD_DELL_LATITUDE_E6320 - default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ + default "8086,0166" if BOARD_DELL_LATITUDE_E6230 \ + || BOARD_DELL_LATITUDE_E6430 \ || BOARD_DELL_LATITUDE_E6530 endif diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index d6fc8eb..cb7bbd5 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E5530 bool "Latitude E5530" +config BOARD_DELL_LATITUDE_E6230 + bool "Latitude E6230" + config BOARD_DELL_LATITUDE_E6330 bool "Latitude E6330" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c new file mode 100644 index 0000000..41fe154 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 0, 1 }, + { 1, 2, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 1, 3 }, + { 1, 2, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 2, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c new file mode 100644 index 0000000..c07e4b1 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio17 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c new file mode 100644 index 0000000..f6876f9 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76df, /* Codec Vendor / Device ID: IDT */ + 0x10280532, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10280532), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb new file mode 100644 index 0000000..798d16e --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb @@ -0,0 +1,17 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x000009e9" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x0532 inherit + + chip southbridge/intel/bd82x6x + register "sata_port_map" = "0x31" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369 Gerrit-Change-Number: 82153 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6330 (Ivy Bridge)
by Nicholas Chin (Code Review) April 30, 2024

April 30, 2024

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82152?usp=email ) Change subject: mb/dell: Add Latitude E6330 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E6330 (Ivy Bridge) Mainboard is QAL70/LA-7741P. I do not physically have this board; it was ported based on autoport output sent to me which I then manually modified. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I827826e9ff8a9a534c50250458b399104478e06c Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb 7 files changed, 286 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/82152/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index baa83ba..49bf225 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -56,6 +56,12 @@ select BOARD_ROMSIZE_KB_12288 select SOUTHBRIDGE_INTEL_C216 +config BOARD_DELL_LATITUDE_E6330 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_C216 + config BOARD_DELL_LATITUDE_E6430 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_12288 @@ -84,6 +90,7 @@ default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 + default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330 default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 @@ -101,13 +108,15 @@ default "e6420" if BOARD_DELL_LATITUDE_E6420 default "e6520" if BOARD_DELL_LATITUDE_E6520 default "e5530" if BOARD_DELL_LATITUDE_E5530 + default "e6330" if BOARD_DELL_LATITUDE_E6330 default "e6430" if BOARD_DELL_LATITUDE_E6430 default "e6530" if BOARD_DELL_LATITUDE_E6530 config VGA_BIOS_ID default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \ || BOARD_DELL_LATITUDE_E5420 - default "8086,0166" if BOARD_DELL_LATITUDE_E5530 + default "8086,0166" if BOARD_DELL_LATITUDE_E5530 \ + || BOARD_DELL_LATITUDE_E6330 default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ || BOARD_DELL_LATITUDE_E5520 \ || BOARD_DELL_LATITUDE_E6220 \ diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index 349ee7f..d6fc8eb 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E5530 bool "Latitude E5530" +config BOARD_DELL_LATITUDE_E6330 + bool "Latitude E6330" + config BOARD_DELL_LATITUDE_E6430 bool "Latitude E6430" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt new file mode 100644 index 0000000..1885674 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c new file mode 100644 index 0000000..5087557 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 2, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 2, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 2, 6 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c new file mode 100644 index 0000000..7775707 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c new file mode 100644 index 0000000..45b0582 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76df, /* Codec Vendor / Device ID: IDT */ + 0x10280533, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10280533), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb new file mode 100644 index 0000000..89c00be --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb @@ -0,0 +1,16 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x0533 inherit + + chip southbridge/intel/bd82x6x + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I827826e9ff8a9a534c50250458b399104478e06c Gerrit-Change-Number: 82152 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6220 (Sandy Bridge)
by Nicholas Chin (Code Review) April 30, 2024

April 30, 2024

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82131?usp=email ) Change subject: mb/dell: Add Latitude E6220 (Sandy Bridge) ...................................................................... mb/dell: Add Latitude E6220 (Sandy Bridge) Mainboard is codenamed Vida. I do not physically have this board; it was ported based on autoport output sent to me which I then manually modified. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb 6 files changed, 284 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/82131/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index 84ffe1d..baa83ba 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -27,6 +27,12 @@ select BOARD_ROMSIZE_KB_6144 select SOUTHBRIDGE_INTEL_BD82X6X +config BOARD_DELL_LATITUDE_E6220 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_10240 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_DELL_LATITUDE_E6320 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_10240 @@ -73,6 +79,7 @@ config MAINBOARD_PART_NUMBER default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420 default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 + default "Latitude E6220" if BOARD_DELL_LATITUDE_E6220 default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320 default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 @@ -89,6 +96,7 @@ config VARIANT_DIR default "e5420" if BOARD_DELL_LATITUDE_E5420 default "e5520" if BOARD_DELL_LATITUDE_E5520 + default "e6220" if BOARD_DELL_LATITUDE_E6220 default "e6320" if BOARD_DELL_LATITUDE_E6320 default "e6420" if BOARD_DELL_LATITUDE_E6420 default "e6520" if BOARD_DELL_LATITUDE_E6520 @@ -102,6 +110,7 @@ default "8086,0166" if BOARD_DELL_LATITUDE_E5530 default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ || BOARD_DELL_LATITUDE_E5520 \ + || BOARD_DELL_LATITUDE_E6220 \ || BOARD_DELL_LATITUDE_E6320 default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ || BOARD_DELL_LATITUDE_E6530 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index ef6a132..349ee7f 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5520 bool "Latitude E5520" +config BOARD_DELL_LATITUDE_E6220 + bool "Latitude E6220" + config BOARD_DELL_LATITUDE_E6320 bool "Latitude E6320" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c new file mode 100644 index 0000000..bb48690 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 0, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + { 1, 0, 6 }, + { 1, 0, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c new file mode 100644 index 0000000..2306e4c --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c new file mode 100644 index 0000000..2085b62 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e7, /* Codec Vendor / Device ID: IDT */ + 0x102804a9, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102804a9), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb new file mode 100644 index 0000000..08fe59b --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb @@ -0,0 +1,15 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x0000046a" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x04a9 inherit + + chip southbridge/intel/bd82x6x + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "sata_port_map" = "0x3b" + + device ref pcie_rp4 off end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c Gerrit-Change-Number: 82131 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6320 (Sandy Bridge)
by Nicholas Chin (Code Review) April 30, 2024

April 30, 2024

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82130?usp=email ) Change subject: mb/dell: Add Latitude E6320 (Sandy Bridge) ...................................................................... mb/dell: Add Latitude E6320 (Sandy Bridge) Mainboard is PAL70/LA-6611P. I do not physically have this board; it was ported based on autoport output sent to me which I then manually modified. This port has not been tested. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. As with the other Dell systems with this EC, this board is assumed to be internally flashable using an EC command that tells it to pull the FDO pin low on the next boot, which also tells the vendor firmware to disable all write protections to the flash [1]. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb 7 files changed, 280 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/82130/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index e6a21ff..84ffe1d 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -27,6 +27,12 @@ select BOARD_ROMSIZE_KB_6144 select SOUTHBRIDGE_INTEL_BD82X6X +config BOARD_DELL_LATITUDE_E6320 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_10240 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_DELL_LATITUDE_E6420 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_10240 @@ -67,6 +73,7 @@ config MAINBOARD_PART_NUMBER default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420 default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 + default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320 default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 @@ -82,6 +89,7 @@ config VARIANT_DIR default "e5420" if BOARD_DELL_LATITUDE_E5420 default "e5520" if BOARD_DELL_LATITUDE_E5520 + default "e6320" if BOARD_DELL_LATITUDE_E6320 default "e6420" if BOARD_DELL_LATITUDE_E6420 default "e6520" if BOARD_DELL_LATITUDE_E6520 default "e5530" if BOARD_DELL_LATITUDE_E5530 @@ -93,7 +101,8 @@ || BOARD_DELL_LATITUDE_E5420 default "8086,0166" if BOARD_DELL_LATITUDE_E5530 default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ - || BOARD_DELL_LATITUDE_E5520 + || BOARD_DELL_LATITUDE_E5520 \ + || BOARD_DELL_LATITUDE_E6320 default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ || BOARD_DELL_LATITUDE_E6530 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index a3fa2b1..ef6a132 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5520 bool "Latitude E5520" +config BOARD_DELL_LATITUDE_E6320 + bool "Latitude E6320" + config BOARD_DELL_LATITUDE_E6420 bool "Latitude E6420" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt new file mode 100644 index 0000000..471a9e2 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c new file mode 100644 index 0000000..bb48690 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 0, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + { 1, 0, 6 }, + { 1, 0, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c new file mode 100644 index 0000000..61f0181 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c new file mode 100644 index 0000000..c87d740 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e7, /* Codec Vendor / Device ID: IDT */ + 0x10280492, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10280492), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb new file mode 100644 index 0000000..350f11f --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb @@ -0,0 +1,12 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000622" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x0492 inherit + + chip southbridge/intel/bd82x6x + register "sata_port_map" = "0x3b" + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46 Gerrit-Change-Number: 82130 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

1 0