coreboot-gerrit April 2024

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[L] Change in coreboot[main]: mb/dell: Add Latitude E5420 (Sandy Bridge)
by Nicholas Chin (Code Review) 30 Apr '24

30 Apr '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82129?usp=email ) Change subject: mb/dell: Add Latitude E5420 (Sandy Bridge) ...................................................................... mb/dell: Add Latitude E5420 (Sandy Bridge) Mainboard is Krug 14". I do not physically have this board; it was ported based on autoport output sent to me which I then manually modified. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I0283653156083768e1fd451bcf539b4e028589f4 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb 7 files changed, 289 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/82129/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index 4e94a7e..e6a21ff 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -17,6 +17,11 @@ select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT +config BOARD_DELL_LATITUDE_E5420 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_6144 + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_DELL_LATITUDE_E5520 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_6144 @@ -60,6 +65,7 @@ default "dell/snb_ivb_latitude" config MAINBOARD_PART_NUMBER + default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420 default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 @@ -74,6 +80,7 @@ default 2 config VARIANT_DIR + default "e5420" if BOARD_DELL_LATITUDE_E5420 default "e5520" if BOARD_DELL_LATITUDE_E5520 default "e6420" if BOARD_DELL_LATITUDE_E6420 default "e6520" if BOARD_DELL_LATITUDE_E6520 @@ -82,7 +89,8 @@ default "e6530" if BOARD_DELL_LATITUDE_E6530 config VGA_BIOS_ID - default "8086,0116" if BOARD_DELL_LATITUDE_E6520 + default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \ + || BOARD_DELL_LATITUDE_E5420 default "8086,0166" if BOARD_DELL_LATITUDE_E5530 default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ || BOARD_DELL_LATITUDE_E5520 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index 7976691..a3fa2b1 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_DELL_LATITUDE_E5420 + bool "Latitude E5420" + config BOARD_DELL_LATITUDE_E5520 bool "Latitude E5520" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt new file mode 100644 index 0000000..98b82fe --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c new file mode 100644 index 0000000..7297921 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + { 1, 1, 6 }, + { 1, 1, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c new file mode 100644 index 0000000..f76b93d --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c new file mode 100644 index 0000000..70e7c2e --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e7, /* Codec Vendor / Device ID: IDT */ + 0x1028049b, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1028049b), + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0x400000f0), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0xd5a30130), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb new file mode 100644 index 0000000..e251d3d --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb @@ -0,0 +1,17 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000c31" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x049b inherit + + chip southbridge/intel/bd82x6x + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" + register "sata_port_map" = "0x3b" + + device ref gbe off end + device ref pcie_rp4 off end + device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0283653156083768e1fd451bcf539b4e028589f4 Gerrit-Change-Number: 82129 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/dell: Add Latitude E5520 (Sandybridge)
by Nicholas Chin (Code Review) 30 Apr '24

30 Apr '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82128?usp=email ) Change subject: mb/dell: Add Latitude E5520 (Sandybridge) ...................................................................... mb/dell: Add Latitude E5520 (Sandybridge) Mainboard is Krug 15". I do not physically have this board; it was ported based on autoport output sent to me which I then manually modified. This was originally tested and found to be working as a standalone board port in Libreboot, but this variant based port in upstream coreboot has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb 7 files changed, 289 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/82128/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index 72bdc96..4e94a7e 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -17,6 +17,11 @@ select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT +config BOARD_DELL_LATITUDE_E5520 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_6144 + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_DELL_LATITUDE_E6420 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_10240 @@ -55,6 +60,7 @@ default "dell/snb_ivb_latitude" config MAINBOARD_PART_NUMBER + default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520 default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 @@ -68,6 +74,7 @@ default 2 config VARIANT_DIR + default "e5520" if BOARD_DELL_LATITUDE_E5520 default "e6420" if BOARD_DELL_LATITUDE_E6420 default "e6520" if BOARD_DELL_LATITUDE_E6520 default "e5530" if BOARD_DELL_LATITUDE_E5530 @@ -77,7 +84,8 @@ config VGA_BIOS_ID default "8086,0116" if BOARD_DELL_LATITUDE_E6520 default "8086,0166" if BOARD_DELL_LATITUDE_E5530 - default "8086,0126" if BOARD_DELL_LATITUDE_E6420 + default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \ + || BOARD_DELL_LATITUDE_E5520 default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ || BOARD_DELL_LATITUDE_E6530 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index c7665ac..7976691 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_DELL_LATITUDE_E5520 + bool "Latitude E5520" + config BOARD_DELL_LATITUDE_E6420 bool "Latitude E6420" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt new file mode 100644 index 0000000..b511e75 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c new file mode 100644 index 0000000..7297921 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + { 1, 1, 6 }, + { 1, 1, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c new file mode 100644 index 0000000..f76b93d --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c new file mode 100644 index 0000000..e2efee3 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e7, /* Codec Vendor / Device ID: IDT */ + 0x1028049a, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1028049a), + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb new file mode 100644 index 0000000..d811832 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb @@ -0,0 +1,17 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000218" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x049a inherit + + chip southbridge/intel/bd82x6x + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }" + register "sata_port_map" = "0x3b" + + device ref gbe off end + device ref pcie_rp4 off end + device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134 Gerrit-Change-Number: 82128 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6520 (Sandy Bridge)
by Nicholas Chin (Code Review) 30 Apr '24

30 Apr '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82127?usp=email ) Change subject: mb/dell: Add Latitude E6520 (Sandy Bridge) ...................................................................... mb/dell: Add Latitude E6520 (Sandy Bridge) Mainboard is PAL60/LA-6562P. The version with an Nvidia dGPU was not tested. I do not physically have this board; it was ported based on autoport output sent to me which I then manually modified. This was originally tested and found to be working as a standalone board port in Libreboot, but this version in upstream coreboot that is set up as a variant has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb 7 files changed, 279 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/82127/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index d278697..72bdc96 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -23,6 +23,12 @@ select MAINBOARD_USES_IFD_GBE_REGION select SOUTHBRIDGE_INTEL_BD82X6X +config BOARD_DELL_LATITUDE_E6520 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_10240 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_DELL_LATITUDE_E5530 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_12288 @@ -50,6 +56,7 @@ config MAINBOARD_PART_NUMBER default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 + default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520 default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 @@ -62,11 +69,13 @@ config VARIANT_DIR default "e6420" if BOARD_DELL_LATITUDE_E6420 + default "e6520" if BOARD_DELL_LATITUDE_E6520 default "e5530" if BOARD_DELL_LATITUDE_E5530 default "e6430" if BOARD_DELL_LATITUDE_E6430 default "e6530" if BOARD_DELL_LATITUDE_E6530 config VGA_BIOS_ID + default "8086,0116" if BOARD_DELL_LATITUDE_E6520 default "8086,0166" if BOARD_DELL_LATITUDE_E5530 default "8086,0126" if BOARD_DELL_LATITUDE_E6420 default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index 257d428..c7665ac 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -3,6 +3,9 @@ config BOARD_DELL_LATITUDE_E6420 bool "Latitude E6420" +config BOARD_DELL_LATITUDE_E6520 + bool "Latitude E6520" + config BOARD_DELL_LATITUDE_E5530 bool "Latitude E5530" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt new file mode 100644 index 0000000..0ef16ee --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c new file mode 100644 index 0000000..2a37091 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + { 1, 0, 6 }, + { 1, 0, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c new file mode 100644 index 0000000..61f0181 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c new file mode 100644 index 0000000..d33eb3b --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e7, /* Codec Vendor / Device ID: IDT */ + 0x10280494, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10280494), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0x400000f2), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb new file mode 100644 index 0000000..98b0e39 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb @@ -0,0 +1,12 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x0494 inherit + + chip southbridge/intel/bd82x6x + register "sata_port_map" = "0x3b" + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec Gerrit-Change-Number: 82127 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/dell: Add Latitude E6420 (Sandy Bridge)
by Nicholas Chin (Code Review) 30 Apr '24

30 Apr '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82126?usp=email ) Change subject: mb/dell: Add Latitude E6420 (Sandy Bridge) ...................................................................... mb/dell: Add Latitude E6420 (Sandy Bridge) Mainboard is PAL50/LA-6591P. The version with an Nvidia dGPU was not tested. I do not physically have this board; it was ported based on autoport output sent to me which I then manually modified. This was originally tested and found to be working as a standalone board port in Libreboot, but this version in upstream coreboot that is set up as a variant has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb 7 files changed, 283 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/82126/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index 183a67b..d278697 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -17,6 +17,12 @@ select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT +config BOARD_DELL_LATITUDE_E6420 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_10240 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_BD82X6X + config BOARD_DELL_LATITUDE_E5530 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_12288 @@ -43,6 +49,7 @@ default "dell/snb_ivb_latitude" config MAINBOARD_PART_NUMBER + default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420 default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 @@ -54,11 +61,15 @@ default 2 config VARIANT_DIR + default "e6420" if BOARD_DELL_LATITUDE_E6420 default "e5530" if BOARD_DELL_LATITUDE_E5530 default "e6430" if BOARD_DELL_LATITUDE_E6430 default "e6530" if BOARD_DELL_LATITUDE_E6530 config VGA_BIOS_ID - default "8086,0166" + default "8086,0166" if BOARD_DELL_LATITUDE_E5530 + default "8086,0126" if BOARD_DELL_LATITUDE_E6420 + default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \ + || BOARD_DELL_LATITUDE_E6530 endif diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index c15ef40..257d428 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_DELL_LATITUDE_E6420 + bool "Latitude E6420" + config BOARD_DELL_LATITUDE_E5530 bool "Latitude E5530" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt new file mode 100644 index 0000000..d3662ee --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c new file mode 100644 index 0000000..0682441 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + { 1, 0, 6 }, + { 1, 0, 7 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c new file mode 100644 index 0000000..943c743 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio30 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c new file mode 100644 index 0000000..b3803b7 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76e7, /* Codec Vendor / Device ID: IDT */ + 0x10280493, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10280493), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb new file mode 100644 index 0000000..6aa6c42 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb @@ -0,0 +1,12 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x0000054f" + register "gpu_pch_backlight" = "0x13121312" + + device domain 0 on + subsystemid 0x1028 0x0493 inherit + + chip southbridge/intel/bd82x6x + register "sata_port_map" = "0x3b" + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394 Gerrit-Change-Number: 82126 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/dell: Add Latitude E5530 (Ivy Bridge)
by Nicholas Chin (Code Review) 30 Apr '24

30 Apr '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82125?usp=email ) Change subject: mb/dell: Add Latitude E5530 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E5530 (Ivy Bridge) Mainboard is QXW10/LA-7902P (UMA). I do not physically have this system; it was ported based on autoport output sent to me which I then manually modified. This was originally tested and found to be working as a standalone board port in Libreboot, but this version in upstream coreboot that is set up as a variant has not been tested. This can be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/Kconfig M src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb 7 files changed, 287 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82125/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig index 0337727..183a67b 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -17,6 +17,11 @@ select SYSTEM_TYPE_LAPTOP select USE_NATIVE_RAMINIT +config BOARD_DELL_LATITUDE_E5530 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 + select SOUTHBRIDGE_INTEL_C216 + config BOARD_DELL_LATITUDE_E6430 select BOARD_DELL_SNB_IVB_LATITUDE_COMMON select BOARD_ROMSIZE_KB_12288 @@ -38,6 +43,7 @@ default "dell/snb_ivb_latitude" config MAINBOARD_PART_NUMBER + default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530 default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530 @@ -48,6 +54,7 @@ default 2 config VARIANT_DIR + default "e5530" if BOARD_DELL_LATITUDE_E5530 default "e6430" if BOARD_DELL_LATITUDE_E6430 default "e6530" if BOARD_DELL_LATITUDE_E6530 diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name index d89185d..c15ef40 100644 --- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_DELL_LATITUDE_E5530 + bool "Latitude E5530" + config BOARD_DELL_LATITUDE_E6430 bool "Latitude E6430" diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt new file mode 100644 index 0000000..3c54b70 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt Binary files differ diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c new file mode 100644 index 0000000..00fd5f6 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 0, 3 }, + { 1, 2, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 }, + { 1, 1, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c new file mode 100644 index 0000000..0599f13 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c new file mode 100644 index 0000000..4c7c36e --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76df, /* Codec Vendor / Device ID: IDT */ + 0x1028053d, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1028053d), + AZALIA_PIN_CFG(0, 0x0a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0421101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0x400000f0), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb new file mode 100644 index 0000000..502cd8f --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb @@ -0,0 +1,18 @@ +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_pch_backlight" = "0x03d003d0" + + device domain 0 on + subsystemid 0x1028 0x053d inherit + + chip southbridge/intel/bd82x6x + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device ref xhci on end + device ref gbe off end + device ref pcie_rp7 on end # BCM5761 Ethernet + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/82125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0 Gerrit-Change-Number: 82125 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6430 (Ivy Bridge)
by Nicholas Chin (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Martin L Roth, Paul Menzel. Hello Martin L Roth, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77444?usp=email to look at the new patch set (#10). Change subject: mb/dell: Add Latitude E6430 (Ivy Bridge) ...................................................................... mb/dell: Add Latitude E6430 (Ivy Bridge) Mainboard is QAL80/LA-7781P (UMA). The version with an Nvidia dGPU model was not tested. This is based on the autoport output with some manual tweaks. The flash is 8MiB + 4MiB, and can be easily accessed by removing the keyboard. It can also be internally flashed by sending a command to the EC, which causes the EC to pull the FDO pin low and the firmware to skip setting up any chipset based write protections [1]. The EC is the SMSC MEC5055, which seems to be compatible with the existing MEC5035 code. Working: - Libgfxinit - USB EHCI debug (left side usb port is HCD index 2, middle port on the right side is HCD index 1) - Keyboard - Touchpad/trackpoint - ExpressCard - Audio - Ethernet - SD card reader - mPCIe WiFi - SeaBIOS 1.16.2 - edk2 (MrChromebox' fork, uefipayload_202306) - Internal flashing using dell-flash-unlock Not working: - S3 suspend: Possibly EC related, DRAM power is getting cut when entering S3 - Physical wireless switch - this triggers an SMI handler in the vendor firmware which sends commands to the EC to enable/disable wireless devices, and has not been reimplemented - Battery reporting - needs ACPI code for the EC - Brightness hotkeys - probably EC related Unknown/untested: - Dock - eSATA - TPM - dGPU on non-UMA model - Bluetooth module (not included on my system) [1] https://gitlab.com/nic3-14159/dell-flash-unlock Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/dell/snb_ivb_latitude/Kconfig A src/mainboard/dell/snb_ivb_latitude/Kconfig.name A src/mainboard/dell/snb_ivb_latitude/Makefile.mk A src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl A src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl A src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl A src/mainboard/dell/snb_ivb_latitude/acpi_tables.c A src/mainboard/dell/snb_ivb_latitude/board_info.txt A src/mainboard/dell/snb_ivb_latitude/cmos.default A src/mainboard/dell/snb_ivb_latitude/cmos.layout A src/mainboard/dell/snb_ivb_latitude/devicetree.cb A src/mainboard/dell/snb_ivb_latitude/dsdt.asl A src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads A src/mainboard/dell/snb_ivb_latitude/mainboard.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt A src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c A src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb 19 files changed, 605 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/77444/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/77444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Gerrit-Change-Number: 77444 Gerrit-PatchSet: 10 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Iru Cai <mytbk920423(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Release bmp_logo during READY_TO_BOOT stage
by Karthik Ramasubramanian (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Andrey Petrov, Matt DeVillier, Ronak Kanabar, Subrata Banik, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82121?usp=email ) Change subject: drivers/intel/fsp2_0: Release bmp_logo during READY_TO_BOOT stage ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > what if any platform decide to not call into fsp notify phases like intel platform starting from adl? in that case, we won't be releasing the bmp logo? notify.c is enabled in ramstage for all platforms. FSP notify phase is skipped at run-time for ADL and MTL. Even there, bmp logo buffer is released since the release operation is done outside the fsp_notify. > can we do the bmp logo release as part of the finalize phase rather trying to bind it against fsp callbacks? Each SoC has soc_finalize callback in Intel platforms whereas AMD has a common soc_finalize callback. This scatters bmp_release_logo throughout the code-base and there are chances where we may forget to release it on certain SoCs. How about registering a callback in silicon_init.c that gets called during BS_PAYLOAD_LOAD as follows: ``` static void release_logo(void *arg_unused) { if (CONFIG(BMP_LOGO)) bmp_release_logo(); } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, release_logo, NULL); ``` This keeps it contained within FSP related code-base and easy to follow through in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/82121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Gerrit-Change-Number: 82121 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 23:28:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Clean up device enablement configuration
by Shuo Liu (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82120?usp=email ) Change subject: soc/intel/xeon_sp: Clean up device enablement configuration ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82120?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493 Gerrit-Change-Number: 82120 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 23:23:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: commonlib: Add skip_atoi()
by Julius Werner (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Maximilian Brune. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78026?usp=email ) Change subject: commonlib: Add skip_atoi() ...................................................................... Patch Set 3: (2 comments) Patchset: PS1: > Its been a while, but I guess that this is what you had in mind? When I said "move into commonlib" I meant commonlib/bsd, so that you can actually share it with libpayload (unless you want to hide this behind CONFIG_GPL... but for a small utility function like this that seems silly). Again, I'm not a lawyer but I would still recommend at least reimplementing this with new code to lower the chance of relicensing concerns, e.g. how about this: ``` unsigned int skip_atoi(char **ptr) { unsigned int result = 0; for (char *str = *ptr; isdigit(str[0]); str++) result = result * 10 + (str[0] - '0'); *ptr = str; } ``` File src/commonlib/string.c: https://review.coreboot.org/c/coreboot/+/78026/comment/cb4d7e71_e2321fe7 : PS3, Line 2: Needs to include `<ctype.h>` for `isdigit()`. (You could also move all of ctype into commonlib if you want. There's a libpayload version there so licensing shouldn't be an issue. Although I think making them static inlines like coreboot does makes more sense.) -- To view, visit https://review.coreboot.org/c/coreboot/+/78026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73cd36ff370e15d5b6242c3b07b14d1724f8ac24 Gerrit-Change-Number: 78026 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 30 Apr 2024 21:54:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/crossgcc: Update GCC from 13.2 to 14.1.0-RC-20240430
by Felix Singer (Code Review) 30 Apr '24

30 Apr '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth. Hello Elyes Haouas, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81683?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/crossgcc: Update GCC from 13.2 to 14.1.0-RC-20240430 ...................................................................... util/crossgcc: Update GCC from 13.2 to 14.1.0-RC-20240430 Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-14.1.0-RC-20240430_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_gnat.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_libcpp.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_libgcc.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14.1.0-RC-20240430_rv32iafc.patch D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14.1.0-RC-20240430.tar.xz.cksum 9 files changed, 11 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81683/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Gerrit-Change-Number: 81683 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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