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Appukuttan V K has uploaded a new patch set (#31) to the change originally created by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/80277?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition.
This appropriate attribute has to be set to all functions calling or
called by the FSP.
- Add FSP 2 Multi Processor Platform Initialization module a function
indirection to ensure that efi_ap_procedure functions are called with
the appropriate C calling convention.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
- This commit adds a function indirection in MP PPI implementation to
ensure FSP callbacks are invoked using the appropriate C calling
convention.
BUG=b:329034258
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M 3rdparty/vboot
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
M src/include/efi/efi_datatype.h
11 files changed, 61 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/31
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81635?usp=email )
Change subject: soc/intel/xeon_sp/spr: Drop microcode constrains
......................................................................
soc/intel/xeon_sp/spr: Drop microcode constrains
For current generation SPR/EMR you need to add at least
3 different microcodes having about 2MiB of size in total.
This doesn't work with the hardcoded offset and size in Kconfig.
Since it's loaded through FIT there's no need to pass it to FSP-T.
Drop the hardcoded locations and place it somewhere in CBFS.
Test: Booted on ibm/sbp1 with microcode confirmed loaded in
bootblock on BSP. All the AP seem also have the correct
microcode version loaded.
Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/spr/Kconfig
1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81635/1
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 2e0ad01..18efbe5 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -76,13 +76,6 @@
allocated at 0xfe800000 (the CAR base) and consumes about 0x150000
bytes of memory.
-config CPU_MICROCODE_CBFS_LOC
- hex
- default 0xffe0fdc0
-
-config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x8c00
config STACK_SIZE
hex
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81634?usp=email )
Change subject: soc/intel/xeon_sp: Compress FSP-S
......................................................................
soc/intel/xeon_sp: Compress FSP-S
Compress FSP-S to save some space in CBFS.
Reduces the size of debug FSP-S by about 25%.
Test: Still boots on ibm/sbp1.
Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/81634/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 78227ed..c26547b 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -15,6 +15,7 @@
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_CAR
select FSP_M_XIP
+ select FSP_COMPRESS_FSP_S_LZ4
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select FSP_T_XIP
select HAVE_SMI_HANDLER
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Change subject: tree: Remove duplicated <stdint.h>
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
Can you add a linter for this? Editors sometimes automatically add headers.
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Change subject: arch/arm: Build test all arm targets with clang
......................................................................
arch/arm: Build test all arm targets with clang
Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept.
Other targets need more aggressive size optimization in the bootblock.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/arm/Kconfig
M src/soc/nvidia/tegra124/Makefile.mk
M src/soc/qualcomm/ipq40xx/Kconfig
M src/soc/qualcomm/ipq40xx/Makefile.mk
M src/soc/qualcomm/ipq806x/Kconfig
M src/soc/rockchip/rk3288/Kconfig
6 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69747/22
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Change subject: tree: Remove duplicated <stdint.h>
......................................................................
tree: Remove duplicated <stdint.h>
<types.h> is supposed to provide <stdint.h>.
Change-Id: Ia68a0dc8fba4a48401e213ebb8356e32f0a019ab
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/cpu/x86/smm/smm_module_loader.c
M src/soc/sifive/fu740/include/soc/sdram.h
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Change subject: mb/google/brox: Update verb table to fix headset detection
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81654/comment/3b2946b2_fbfa3f83 :
PS1, Line 16: under runtime suspend
> reframed.
Runtime suspend here is referring to audio DSP. In legacy hda driver it is mentioned as a parameter as `power_save`. We may actually state this clearly.
Commit Message:
https://review.coreboot.org/c/coreboot/+/81654/comment/16a23cb5_e2d450b3 :
PS2, Line 4: poornima
This is still left unmodified.
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Change subject: util/crossgcc/buildgcc: Use Intel mirror for ACPICA
......................................................................
Patch Set 7:
(1 comment)
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/80721/comment/08882bfd_0c70dac0 :
PS7, Line 77: 783534
looks like this works only for version "20230628"
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