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Change subject: acpi: Add acpigen_write_OSC_pci_domain
......................................................................
Patch Set 19:
(1 comment)
File src/acpi/acpigen_pci.c:
https://review.coreboot.org/c/coreboot/+/81375/comment/038c8b04_f24e64d2 :
PS12, Line 348: __weak unsigned long get_granted_pci_features(const struct device *domain)
: {
: return 0;
: }
:
: __weak unsigned long get_granted_cxl_features(const struct device *domain)
: {
: return 0;
: }
> Pass parameters instead of using weak functions looks good. […]
i'd say that if a soc wants to use the functions added in this patch, it should provide the functions it calls, so there's no need for the weak functions here. if the functions that call the weak functions aren't called, the linker won't be unhappy about the functions being called not being implemented
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Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 36:
(1 comment)
File src/soc/intel/xeon_sp/gnr/cpu.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/76398080_3f4c55e9 :
PS36, Line 61: {X86_VENDOR_INTEL, CPUID_GRANITERAPIDS},
those two lines are missing cpu match mask struct element
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Change subject: riscv/opensbi: make the opensbi payload a flat binary
......................................................................
Patch Set 4:
(2 comments)
File src/arch/riscv/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/81632/comment/ac0f96e4_eb3d3874 :
PS4, Line 178: $(OPENSBI_CBFS)-compression := non
is it executed in place? or why not compress?
File src/mainboard/emulation/qemu-riscv/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/81632/comment/b12468ce_24018e09 :
PS4, Line 9: #define ROMSTAGESIZE 0
Why this change?
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Change subject: mb/google/brya/var/sundance: Add GPIO table
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/brya/variants/sundance/Makefile.inc:
PS5:
the file name should be Makefile.mk and not Makefile.inc; I think in January we changed the file extension used by the makefiles
https://review.coreboot.org/c/coreboot/+/81613/comment/0076842a_aae2f5a2 :
PS5, Line 1: # SPDX-License-Identifier: GPL-2.0-only
> NO, There's no empty line after this line.
at least in the other coreboot code there's an empty line after the spdx header; adding Martin to the review who might know more about this
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Change subject: drivers/mipi: Fine tune clock for BOE_NV110WUM_L60
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81438/comment/ec24df28_9d7154c7 :
PS4, Line 11: Just keep consistent with the Linux kernel panel driver
: configuration.
> https://chromium-review.googlesource. […]
Thank you. This should be part of the commit message.
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Dinesh Gehlot has uploaded a new patch set (#7) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/libgfxinit/+/67800?usp=email )
Change subject: common: Begin Alder Lake integration
......................................................................
common: Begin Alder Lake integration
Alder Lake uses the same generation of igfx engine as Tiger Lake,
therefore the changes required to support ADL-P are minor. This patch
starts with PCI device detection.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I3258a125d4b76929673eea5406d26575f9fbd535
---
M common/hw-gfx-gma-config.ads.template
M configs/alderlake
2 files changed, 17 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/00/67800/7
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