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Change subject: acpi: Add acpi_device_write_dsd_gpio for public
......................................................................
Patch Set 6:
(3 comments)
File src/acpi/device.c:
https://review.coreboot.org/c/coreboot/+/81788/comment/ad4342fc_b0df7c49 :
PS6, Line 46:
> I would like to add check the pointer in case of NULL pointer.
+1
https://review.coreboot.org/c/coreboot/+/81788/comment/233b0fa1_985f6ff6 :
PS6, Line 51: ret = *curr_index;
ret = *curr_index++;
https://review.coreboot.org/c/coreboot/+/81788/comment/a9515fbc_ebb8c80a :
PS6, Line 52: (*curr_index)++;
don't need
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Change subject: acpi: Add acpi_device_write_dsd_gpio for public
......................................................................
Patch Set 6:
(1 comment)
File src/acpi/device.c:
https://review.coreboot.org/c/coreboot/+/81788/comment/61da62ca_265e0f43 :
PS6, Line 46:
I would like to add check the pointer in case of NULL pointer.
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Patch Set 2: Code-Review+2
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Change subject: util/ifdtool: Add support for checking GPR0 status
......................................................................
Patch Set 5:
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/81928/comment/ef9d9bd8_d3999a11 :
PS4, Line 1802: reg.data.write_protect_en
> >> Should we also check that the range is set correctly? E.g. […]
My concern was people might assume they can use this to validate that GPR0 is set correctly, e.g. use it in a factory test at some point in the future. So it seems safer to check the range as well. But I don't have a strong preference, so feel free to leave it as is.
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81886?usp=email )
Change subject: arch/x86: Prevent .text/.init overlap with older linkers
......................................................................
arch/x86: Prevent .text/.init overlap with older linkers
Add Kconfig option `X86_BOOTBLOCK_EXTRA_PROGRAM_SZ` to reserve extra
space, avoiding overlap between .text and .init sections when using
older linkers (binutils 2.3x). Default is 1024 bytes (1 KiB) for
ChromeOS, 0 otherwise.
BUG=b:332445618
TEST=Built and booted google/rex (32-bit/64-bit).
Change-Id: I019bf6896d84b2a84dff6f22323f0f446c0740b5
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81886
Reviewed-by: Dinesh Gehlot <digehlot(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
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Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/bootblock.ld
2 files changed, 12 insertions(+), 1 deletion(-)
Approvals:
Eric Lai: Looks good to me, approved
Angel Pons: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
build bot (Jenkins): Verified
Dinesh Gehlot: Looks good to me, approved
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index d2ae320..7d25561 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -412,4 +412,15 @@
If not set, both CPU and SoC physical address width are
assume to be the same.
+config X86_BOOTBLOCK_EXTRA_PROGRAM_SZ
+ int
+ default 1024 if CHROMEOS
+ default 0
+ help
+ Add extra space to prevent overlap between .text and .init sections.
+ This is necessary for older linkers (pre-binutils 2.4x) like those used
+ on ChromeOS platforms.
+
+ The default value is 1024 bytes (1 KiB) for ChromeOS and 0 for other platforms.
+
endif
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
index 73a3d18..1f44d6a 100644
--- a/src/arch/x86/bootblock.ld
+++ b/src/arch/x86/bootblock.ld
@@ -26,7 +26,7 @@
INCLUDE "bootblock/lib/program.ld"
- PROGRAM_SZ = SIZEOF(.text) + SIZEOF(.data);
+ PROGRAM_SZ = SIZEOF(.text) + SIZEOF(.data) + CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ;
. = MIN(_ECFW_PTR, MIN(_ID_SECTION, _FIT_POINTER)) - EARLYASM_SZ;
. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(16);
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Change subject: acpi: Add acpi_device_write_dsd_gpio for public
......................................................................
Patch Set 6:
(1 comment)
File src/acpi/device.c:
https://review.coreboot.org/c/coreboot/+/81788/comment/3fc121d6_6ea4331b :
PS5, Line 42: I2C
> please update the comment. […]
Done
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Hello Cliff Huang, Dolan Liu, Eric Lai, Lance Zhao, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81788?usp=email
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Verified+1 by build bot (Jenkins)
Change subject: acpi: Add acpi_device_write_dsd_gpio for public
......................................................................
acpi: Add acpi_device_write_dsd_gpio for public
Make sure it can be use for other driver.
BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.
Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
---
M src/acpi/device.c
M src/drivers/i2c/generic/generic.c
M src/include/acpi/acpi_device.h
3 files changed, 21 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/81788/6
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Change subject: mb/google/nissa/var/glassway: Add New SPD ID for supported memory parts
......................................................................
Patch Set 2: Code-Review+2
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