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Hello Cliff Huang, Dolan Liu, Eric Lai, Lance Zhao, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: acpi: Add acpi_device_write_dsd_gpio for public
......................................................................
acpi: Add acpi_device_write_dsd_gpio for public
Make sure it can be use for other driver.
BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.
Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
---
M src/acpi/device.c
M src/drivers/i2c/generic/generic.c
M src/include/acpi/acpi_device.h
3 files changed, 23 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/81788/10
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81954?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: cpu/intel/microcode: Defer microcode patching until after DRAM init
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81954/comment/24b005cd_71e053dd :
PS1, Line 9: Follows Intel SoC recommendation to avoid potential cache contention
: issues during early (pre-DRAM) microcode loading.
Please document the source, maybe even section in the datasheet.
https://review.coreboot.org/c/coreboot/+/81954/comment/57e93843_693b11ed :
PS1, Line 17: [DEBUG] microcode: sig=0xa06a4 pf=0x80 revision=0x19
: [INFO ] CBFS: Found 'cpu_microcode_a06a4.bin' @0x1d9c0 size 0x21400
: in mcache @0xfef89680
: [INFO ] VB2:vb2_digest_init() 136192 bytes, hash algo 2, HW
: acceleration enabled
: [INFO ] microcode: load microcode patch
: [ERROR] microcode: Update failed
Indent by four spaces and do not wrap the lines. Hopefully, the linter is going to recognize it as code block.
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Change subject: util/ifdtool: Add support for checking GPR0 status
......................................................................
Patch Set 5:
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/81928/comment/6709dc48_79179cb6 :
PS4, Line 1802: reg.data.write_protect_en
Hi Reka,
> My concern was people might assume they can use this to validate that GPR0 is set correctly, e.g. use it in a factory test at some point in the future. So it seems safer to check the range as well.
You mean not only check `reg.data.write_protect_en` but check the whole GPR0 register?
Like function `enable_gpr0()` do, maybe we can use same method like this to check GPR0 register?
```c
if (calculate_gpr0_range(image, size, &gpr0_range_start, &gpr0_range_end))
exit(EXIT_FAILURE);
reg.data.start = (gpr0_range_start >> 12) & 0x7fff;
reg.data.end = (gpr0_range_end >> 12) & 0x7fff;
reg.data.read_protect_en = 0;
reg.data.write_protect_en = 1;
```
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Change subject: soc/amd/glinda : Add support for A0 and B0 steppings
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81887/comment/8d892482_1df764ae :
PS2, Line 7: soc/amd/glinda :
Please remove the space before the colon.
https://review.coreboot.org/c/coreboot/+/81887/comment/c1f2c634_0d3e0883 :
PS2, Line 9: Update the A0 and B0 stepping IDs in CPU table
Please mention the datasheet name and revision.
File src/soc/amd/glinda/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/81887/comment/5cbb9822_92eb0876 :
PS2, Line 6:
Use tabs?
https://review.coreboot.org/c/coreboot/+/81887/comment/10eedbfa_5aef0685 :
PS2, Line 6: 0x1A
Lowercase?
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Change subject: sb/intel/bd82x6x/pch.asl: Remove GPIO configuration access
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/asus/p8z77-m[_pro]: Blink power LED during suspend
......................................................................
Patch Set 1: Code-Review+2
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Change subject: sb/intel/bd82x6x/pch.asl: Break out GPIO blink field
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Patch Set 1: Code-Review+2
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Change subject: mb/asus/p8z77-m[_pro]: Correct PCH GPIO config
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Patch Set 1: Code-Review+2
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Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
Patch Set 20:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81773/comment/802a4851_ad09e3b9 :
PS20, Line 9: .The
Please add a space.
File src/drivers/i2c/rt5645/rt5645.c:
https://review.coreboot.org/c/coreboot/+/81773/comment/fec5457b_14f9c7e3 :
PS20, Line 86: printk(BIOS_INFO, "%s: %s\n", path, config->desc ? : dev->chip_ops->name);
Could that log message be more descriptive, so users can deal with it?
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