coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: mb/google/beltino: Set initial fan PWM to 30%
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81513?usp=email ) Change subject: mb/google/beltino: Set initial fan PWM to 30% ...................................................................... mb/google/beltino: Set initial fan PWM to 30% Recent changes to the ITE 8772F SIO code caused the initial fan PMW to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot google/beltino to payload, verify fan noise is negligable Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/81513/1 diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index d96ee11..9dacd6d 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -84,6 +84,7 @@ register "TMPIN3.mode" = "THERMAL_PECI" # Enable FAN2 register "FAN2.mode" = "FAN_SMART_SOFTWARE" + register "FAN2.smart.pwm_start" = "30" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81513?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Gerrit-Change-Number: 81513 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Cliff Huang, CoolStar, Felix Held, Lance Zhao, Matt DeVillier, Paul Menzel, Tim Wawrzynczak. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Is AMD going to work on an official driver, or just buy the one from CoolStar, and publish it as FLO […] this has nothing to do with AMD (or Intel), it's an ACPI device for the coreboot/cbmem table. -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 25 Mar 2024 13:47:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: superio/ite: Unify it8772f with common code
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Joel Linn, Michał Żygowski, MrChromebox, Nico Huber, Piotr Król. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81310?usp=email ) Change subject: superio/ite: Unify it8772f with common code ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/beltino/devicetree.cb: https://review.coreboot.org/c/coreboot/+/81310/comment/b3931820_c6a45e90 : PS4, Line 86: register "FAN2.mode" = "FAN_SMART_SOFTWARE" > Matt, would you have a Beltino at hand to test if this feels like a regression? […] in my tree, I have it set to 30% at startup, just so we don't have zero fan control until ACPI takes over. I'll push a follow-on patch for all the IT8772F ChromeOS devices setting it there -- To view, visit https://review.coreboot.org/c/coreboot/+/81310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Gerrit-Change-Number: 81310 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Attention: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 13:46:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: acpi: Add acpigen_write_OSC_pci_domain ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81375/comment/d4dea873_7dd5cdb6 : PS9, Line 7: soc_acpigen_write_OSC_pci_domain > Remove `soc_` prefix since this is in `src/acpi`. Done File src/acpi/acpigen_pci.c: https://review.coreboot.org/c/coreboot/+/81375/comment/73ddc03e_a49af11e : PS9, Line 69: soc_acpigen_OSC_handle_pcie_request > Remove `soc_` prefix since this is in `src/acpi`. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 13:01:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81375?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: acpi: Add acpigen_write_OSC_pci_domain ...................................................................... acpi: Add acpigen_write_OSC_pci_domain Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/gnr/soc_acpi.c 3 files changed, 312 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81375/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Felix Singer, Michał Żygowski, Paul Menzel. Alicja Michalska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email ) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... Patch Set 2: (28 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80853/comment/3dbdee87_7b187349 : PS1, Line 25: even though I force-disabled it, I'm still getting AERs > That's because AER is still enabled: […] No, of course not. I want to fix the issue, not hide it 😜 https://review.coreboot.org/c/coreboot/+/80853/comment/41fa55d5_cc0e8bc1 : PS1, Line 35: haven't enabled > singular: hasn’t enabled […] Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/b38ad7ae_1c89ab7a : PS1, Line 39: : Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot : the machine without `pcie_aspm=off` parameter: : - BadTLP : - BadDLLP : - Timeout : - Rollover : : Adjusting LaneEq's didn't change anything, all settings are configured : in (mostly) the same way as they were on stock firmware. > Without proper `PcieClkSrcClkReq` settings, the most you can get is ASPM L0s. […] Yes, that's true. I have disabled all ASPM I could find, though: ``` config PCIEXP_ASPM default n config PCIEXP_CLK_PM default n config PCIEXP_L1_SUB_STATE default n ``` https://review.coreboot.org/c/coreboot/+/80853/comment/b968ac9d_95c010f0 : PS1, Line 50: Starting to suspect Intel's FSP might be buggy, as I haven't had those : issues when I initially started working on this project when 4.20 tree : was current. > Would be nice if you could bisect in some way. Will try. I had suffered a lot of health issues in recent months (especially in March), so I didn't feel well enough to dedicate time to this port. Definitely want to get to the bottom of it now that I'm feeling better though 😊 File src/mainboard/erying/Kconfig: PS1: > Missing […] Done File src/mainboard/erying/Kconfig.name: PS1: > Missing […] Done File src/mainboard/erying/tgl/Kconfig: PS1: > Missing […] Done https://review.coreboot.org/c/coreboot/+/80853/comment/c847a34a_4953491e : PS1, Line 24: config DIMM_SPD_SIZE : default 512 > 512 is the default, remove. Acknowledged File src/mainboard/erying/tgl/Kconfig.name: PS1: > Missing […] Done File src/mainboard/erying/tgl/bootblock.c: PS1: > Use tabs instead of spaces. Done File src/mainboard/erying/tgl/devicetree.cb: PS1: > Remove execute bit. Done https://review.coreboot.org/c/coreboot/+/80853/comment/74a41f13_35096ce3 : PS1, Line 6: .tdp_pl1_override = 45, : . > Add one more tab Done https://review.coreboot.org/c/coreboot/+/80853/comment/6a8bdd13_64ae4869 : PS1, Line 11: .tdp_pl1_override = 45, : . > Add one more tab Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/a339ab75_567eb5f6 : PS1, Line 16: # FSP configuration > Seems superfluous Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/45ad9a4d_c6bd5db3 : PS1, Line 22: # IT8613E doesn't support s0ix specification, only S3 is possible. : # Sleep is broken, supposedly RAM loses power in S3 state. : register "s0ix_enable" = "0" > Rather add that information to the commit message and later to the documentation instead of here. Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/960f7b91_3739c9a4 : PS1, Line 26: # Power > Seems superfluous Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/19a9478b_ce99cdd9 : PS1, Line 35: device ref system_agent on end > Equivalent to chipset dt, remove. Done https://review.coreboot.org/c/coreboot/+/80853/comment/e32321f5_a22f0b50 : PS1, Line 37: # [01.0] PCI-E x16 4.0 (SoC) > Please don't document the PCI numbers. It leads to copy/paste issues and thus wrong documentation. […] Done https://review.coreboot.org/c/coreboot/+/80853/comment/c5bd97c4_00097a92 : PS1, Line 43: # [02.0] TigerLake-H GT1 > Most of the comments seem superfluous since the alias names are used. Remove. Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/2fdc3b62_860fe864 : PS1, Line 70: [0] = USB2_PORT_MID(OC0), /* Rear, bottom right */ : [1] = USB2_PORT_MID(OC0), /* Rear, bottom left */ : [2] = USB2_PORT_MID(OC2), /* NIC left */ : [3] = USB2_PORT_MID(OC2), /* NIC right */ : [4] = USB2_PORT_MID(OC2), /* Front Panel 1 */ : [5] = USB2_PORT_MID(OC2), /* Front Panel 2 */ : [8] = USB2_PORT_MID(OC0), /* Front Panel 1 (USB3) */ : [9] = USB2_PORT_MID(OC0), /* Front Panel 2 (USB3) */ : [10] = USB2_PORT_MID(OC0), /* Rear, top left */ : > Add one more tab Done https://review.coreboot.org/c/coreboot/+/80853/comment/ca6fa7f3_beacb4ed : PS1, Line 83: [0] = USB3_PORT_DEFAULT(OC0), /* Rear, bottom right */ : [1] = USB3_PORT_DEFAULT(OC0), /* Rear, bottom left */ : [2] = USB3_PORT_DEFAULT(OC0), /* Front Panel 1 */ : [3] = USB3_PORT_DEFAULT(OC0), /* Front Panel 2 */ : [4] = USB3_PORT_DEFAULT(OC0), /* Rear, top left */ : > Add one more tab Done https://review.coreboot.org/c/coreboot/+/80853/comment/4d122c7b_d6d161ee : PS1, Line 96: device ref heci1 off end > Equivalent to chipset dt, remove. Done https://review.coreboot.org/c/coreboot/+/80853/comment/2d516bc7_a42e957b : PS1, Line 222: register "PchHdaDspEnable" = "0" > Avoid setting boolean options to 0, as it's the default. […] ACK, I left it while debugging and forgot to remove it. https://review.coreboot.org/c/coreboot/+/80853/comment/20c252de_a20fe757 : PS1, Line 225: device ref fast_spi off end > Avoid adding devices which have the same state as the definitions in the chipset devices tree. […] Done File src/mainboard/erying/tgl/gpio.h: https://review.coreboot.org/c/coreboot/+/80853/comment/3f92f3ca_de961a86 : PS1, Line 32: /* GPIO */ > Remove comments for GPIOs which are NC. Done File src/mainboard/erying/tgl/ramstage.c: PS1: > Remove execute bit. Done File src/mainboard/erying/tgl/romstage_fsp_params.c: PS1: > Remove execute bit. Done https://review.coreboot.org/c/coreboot/+/80853/comment/a14aefff_46f08293 : PS1, Line 99: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); > Is there a reason you do GPIO configuration before FSP-M runs? FSP might reconfigure GPIOs, so you s […] Not really, will take a look. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 25 Mar 2024 12:51:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Alicja Michalska. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80853?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E RS232) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports (somewhat) - PCI-E Resizable BAR (ReBAR) - VT-x (PCI-E passtrough, broken on stock) WIP/Broken: - PCI-E ASPM (even though I force-disabled it, I'm still getting AERs) - M.2 NGFF WiFi (should be working, but I lost my WiFi card while moving) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (simple fix, need to re-configure GPIOs) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor haven't enabled any protections on SPI chip. I'd like to get ASPM working as it makes big difference in idle power consumtion (25 vs 60W measured from the wall at 230V). Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot the machine without `pcie_aspm=off` parameter: - BadTLP - BadDLLP - Timeout - Rollover Adjusting LaneEq's didn't change anything, all settings are configured in (mostly) the same way as they were on stock firmware. Starting to suspect Intel's FSP might be buggy, as I haven't had those issues when I initially started working on this project when 4.20 tree was current. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.7.4) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.inc A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 857 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Add soc_acpigen_write_OSC_pci_domain
by Patrick Rudolph (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Shuo Liu, Tim Chu, Tim Wawrzynczak. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: acpi: Add soc_acpigen_write_OSC_pci_domain ...................................................................... Patch Set 9: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81375/comment/c1fa631e_9f0fbb1a : PS9, Line 7: soc_acpigen_write_OSC_pci_domain Remove `soc_` prefix since this is in `src/acpi`. File src/acpi/acpigen_pci.c: https://review.coreboot.org/c/coreboot/+/81375/comment/81026bd8_050b1a70 : PS9, Line 69: soc_acpigen_OSC_handle_pcie_request Remove `soc_` prefix since this is in `src/acpi`. -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 11:51:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by Paul Menzel (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Cliff Huang, CoolStar, Felix Held, Lance Zhao, Matt DeVillier, Matt DeVillier, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: nd PS1: > yes, it's just a cosmetic issue, but if i didn't know the details and reasoning behind this, i'd exp […] Is AMD going to work on an official driver, or just buy the one from CoolStar, and publish it as FLOSS and put it on Windows update? -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 25 Mar 2024 10:55:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/coreboot/+/81312/comment/c1c2e3f5_317671db : PS16, Line 192: #if CONFIG(SOC_INTEL_HAS_CXL) > You would have to declare it, e.g. in line 185: […] I tried this change and it works, but for me seems a bit confusing, since create_cxl_domains is regarded as a static function when CONFIG(SOC_INTEL_HAS_CXL) is selected, but as a global function when CONFIG(SOC_INTEL_HAS_CXL) is not selected. Maybe let us keep the current implementation? -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 17 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 10:48:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2024