coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[L] Change in coreboot[main]: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81377?usp=email to look at the new patch set (#7). Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation ...................................................................... soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation Domain SSDT is dynamically generated by soc_pci_domain_fill_ssdt. SPR has 2 SKUs, XCC and MCC. Dynamic domain SSDT generation could better fit both. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. TEST=intel/archercity CRB Linux ACPI host bridge parsing logs are kept the same before and after, with some minor issue fixed. Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h D src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl D src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl D src/soc/intel/xeon_sp/spr/acpi/iiostack.asl D src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl D src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c 9 files changed, 84 insertions(+), 322 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81377/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Gerrit-Change-Number: 81377 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: UPSTREAM: mb/corsola/kyogre: Add new board 'Kyogre'
by Yidi Lin (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Kei Hiroyoshi, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81218?usp=email ) Change subject: UPSTREAM: mb/corsola/kyogre: Add new board 'Kyogre' ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81218/comment/4c67eac6_a47def45 : PS3, Line 7: mb/corsola/kyogre: mb/google/corsola: https://review.coreboot.org/c/coreboot/+/81218/comment/37211d07_7bccd285 : PS3, Line 9: Kinger Kingler -- To view, visit https://review.coreboot.org/c/coreboot/+/81218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Gerrit-Change-Number: 81218 Gerrit-PatchSet: 3 Gerrit-Owner: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kenny Pan <kennypan(a)google.com> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 06:08:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Subrata Banik (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81436/comment/5516edb0_3829c564 : PS3, Line 12: appreciate if you can share the output of soc_power_limits_config w/o and w/ your CL. I can understand it fixed a hidden issue but would be good if we can call that out in commit msg. File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c: https://review.coreboot.org/c/coreboot/+/81436/comment/b8302a18_92695442 : PS3, Line 25: sa_pci_id what if `sa_pci_id` is 0xffff ? -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 25 Mar 2024 06:07:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: UPSTREAM: mb/corsola/kyogre: Add new board 'Kyogre'
by Knox Chiou (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Kei Hiroyoshi, Yidi Lin, Yu-Ping Wu. Knox Chiou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81218?usp=email ) Change subject: UPSTREAM: mb/corsola/kyogre: Add new board 'Kyogre' ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81218/comment/66d93c4a_50583b62 : PS3, Line 7: UPSTREAM: mb/corsola/kyogre: Add new board 'Kyogre' Remove the UPSTREAM prefix since it's internal use only. -- To view, visit https://review.coreboot.org/c/coreboot/+/81218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Gerrit-Change-Number: 81218 Gerrit-PatchSet: 3 Gerrit-Owner: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kenny Pan <kennypan(a)google.com> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 06:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Move domain resources adding to their creation
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81435?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Move domain resources adding to their creation ...................................................................... soc/intel/xeon_sp: Move domain resources adding to their creation Domain resources adding is moved from read_resources to domain creation so that late HOB lookup could be avoided. TEST=intel/archercity CRB Change-Id: Iba58dc9ac1d2e7d07004ee2bb0cc76b273d37e99 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 4 files changed, 28 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81435/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba58dc9ac1d2e7d07004ee2bb0cc76b273d37e99 Gerrit-Change-Number: 81435 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81377?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation ...................................................................... soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation Domain SSDT is dyanmically generated by soc_pci_domain_fill_ssdt. SPR has 2 SKUs, XCC and MCC. Dynamic domain SSDT generation could better fit both. One possible side-effect might be the extra performance cost for generating these tables, which should not bring big impact on high performance server CPUs. TEST=intel/archercity CRB Linux ACPI host bridge parsing logs are kept the same before and after, with some minor issue fixed. Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h D src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl D src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl D src/soc/intel/xeon_sp/spr/acpi/iiostack.asl D src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl D src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c 9 files changed, 84 insertions(+), 322 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81377/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba Gerrit-Change-Number: 81377 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[main]: acpi: Add soc_acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81375?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: acpi: Add soc_acpigen_write_OSC_pci_domain ...................................................................... acpi: Add soc_acpigen_write_OSC_pci_domain Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/gnr/soc_acpi.c 3 files changed, 301 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81375/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: acpi: Add soc_pci_domain_fill_ssdt
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Jincheng Li, Lance Zhao, Tim Wawrzynczak. Hello Cliff Huang, Jincheng Li, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81373?usp=email to look at the new patch set (#5). Change subject: acpi: Add soc_pci_domain_fill_ssdt ...................................................................... acpi: Add soc_pci_domain_fill_ssdt soc_pci_domain_fill_ssdt does SoC layer domain SSDT generation, e.g. device object creation and some SoC specific methods. SoC specific generation is placed ahead of generic content generation, so that the device object could be created before being referenced in the generic contents. A default null weak implementation is provided. For platforms with static domain SoC SSDT generation, just use the default weak implementation. For platforms with dynamic domain SoC SSDT generation, the default method should be overridden. Dynamic domain SSDT generation is not a must. It would be helpful for some SoC codes to better fit multiple SKUs and with strong CPU performance to run table generation logics. Change-Id: I893eb64c776e78f46737072b475acde5e32a796a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/acpi/acpigen_pci_root_resource_producer.c M src/include/acpi/acpigen_pci.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81373/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I893eb64c776e78f46737072b475acde5e32a796a Gerrit-Change-Number: 81373 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/rex: Enable Intel RMT+
by Gaggery Tsai (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77684?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex: Enable Intel RMT+ ...................................................................... mb/google/rex: Enable Intel RMT+ This patch enables Intel RMT+ support for Rex platform. BUG=b:293441360 TEST=1. Build an image with this patch 2. Deploy the image to a Rex device 3. Ensure /sys/firmware/acpi/tables/BDAT is exported from kernel. Change-Id: I4e56c32cee1ce8c10b9da9d0123cbd13eaf9d8d3 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/77684/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/77684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e56c32cee1ce8c10b9da9d0123cbd13eaf9d8d3 Gerrit-Change-Number: 77684 Gerrit-PatchSet: 11 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: soc/intel/mtl: Add Intel RMT+ support
by Gaggery Tsai (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Jérémy Compostella, Kane Chen, Karthik Ramasubramanian, Krishna P Bhat D, Pratikkumar V Prajapati, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tarun, Tarun Tuli, V Sowmya, Wonkyu Kim. Hello Anil Kumar K, Bora Guvendik, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jamie Ryu, Jérémy Compostella, Kane Chen, Kapil Porwal, Krishna P Bhat D, Pratikkumar V Prajapati, Ravishankar Sarawadi, Ronak Kanabar, Subrata Banik, Tarun, Tarun Tuli, V Sowmya, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77257?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/mtl: Add Intel RMT+ support ...................................................................... soc/intel/mtl: Add Intel RMT+ support This patch adds Intel RMT+ (Rank Margin Test Plus) support on MTL. BUG=b:293441360 TEST=1. Build an image with SOC_INTEL_RMT_PLUS_IN_DEV_MODE enabled 2. Deploy the image to a Rex device 3. Ensure /sys/firmware/acpi/tables/BDAT is exported from kernel. Change-Id: Ieeaa8faf059bed90fca5029d4274db431b4eebea Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/soc/intel/meteorlake/meminit.c M src/soc/intel/meteorlake/romstage/fsp_params.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/77257/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/77257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieeaa8faf059bed90fca5029d4274db431b4eebea Gerrit-Change-Number: 77257 Gerrit-PatchSet: 18 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024