coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: vc/wuffs: Fix compiling for 64bit and clang
by Elyes Haouas (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Patrick Georgi. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81382?usp=email ) Change subject: vc/wuffs: Fix compiling for 64bit and clang ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23ef29010d60bd543e48af032795ec9fc2ff9ecb Gerrit-Change-Number: 81382 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 25 Mar 2024 03:06:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: add new SBI calls
by ron minnich (Code Review) 24 Mar '24

24 Mar '24

ron minnich has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81294?usp=email ) Change subject: arch/riscv: add new SBI calls ...................................................................... arch/riscv: add new SBI calls This is just a start. We are playing catch up. 7 down, 70+ to go. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81294 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/arch/riscv/sbi.c 1 file changed, 70 insertions(+), 5 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index 8bf21b7..2ef7625 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <mcall.h> #include <stdint.h> #include <arch/exception.h> @@ -49,6 +50,54 @@ return 0; } +static void print_sbi_trap(uintptr_t trap) +{ + switch (trap) { + case SBI_SHUTDOWN: + printk(BIOS_EMERG, "SBI_SHUTDOWN\n"); + break; + case SBI_REMOTE_SFENCE_VMA_ASID: + printk(BIOS_EMERG, "SBI_REMOTE_SFENCE_VMA_ASID\n"); + break; + case SBI_REMOTE_SFENCE_VMA: + printk(BIOS_EMERG, "SBI_REMOTE_SFENCE_VMA\n"); + break; + case SBI_REMOTE_FENCE_I: + printk(BIOS_EMERG, "SBI_REMOTE_FENCE_I\n"); + break; + case SBI_SEND_IPI: + printk(BIOS_EMERG, "SBI_SEND_IPI\n"); + break; + case SBI_CLEAR_IPI: + printk(BIOS_EMERG, "SBI_CLEAR_IPI\n"); + break; + case SBI_CONSOLE_GETCHAR: + printk(BIOS_EMERG, "SBI_CONSOLE_GETCHAR\n"); + break; + case SBI_CONSOLE_PUTCHAR: + printk(BIOS_EMERG, "SBI_CONSOLE_PUTCHAR\n"); + break; + case SBI_SET_TIMER: + printk(BIOS_EMERG, "SBI_SET_TIMER\n"); + break; + case SBI_BASE_EXTENSION: + printk(BIOS_EMERG, "SBI_BASE_EXTENSION\n"); + break; + default: + printk(BIOS_EMERG, "%lx is an unknown SBI trap\n", trap); + break; + } +} + +/* + * These are the default SBI extension values. + * They can be overridden, by specialized code, + * but since this is a GPL SBI, it may be better + * that they evolve as we extend this SBI. + * over time, the will be updated. + */ +int sbi_features[] = {1, 0, 0, 0, 0, 0, 0}; + /* * sbi is triggered by the s-mode ecall * parameter : register a0 a1 a2 @@ -58,11 +107,14 @@ void handle_sbi(struct trapframe *tf) { uintptr_t ret = 0; + uintptr_t sbiret = 0; uintptr_t arg0 = tf->gpr[10]; __maybe_unused uintptr_t arg1 = tf->gpr[11]; - uintptr_t which = tf->gpr[17]; + uintptr_t fid = tf->gpr[16]; + uintptr_t eid = tf->gpr[17]; + uintptr_t retpc = read_csr(mepc) + 4; - switch (which) { + switch (eid) { case SBI_SET_TIMER: #if __riscv_xlen == 32 ret = sbi_set_timer(arg0 + ((uint64_t)arg1 << 32)); @@ -96,10 +148,23 @@ case SBI_SHUTDOWN: ret = send_ipi((uintptr_t *)arg0, IPI_SHUTDOWN); break; + case SBI_BASE_EXTENSION: + /* zero is an allowed return value for most features, + * and the only required one is feature 0. + * So this test will return legal values + * for all possible values of fid. + */ + if (fid < ARRAY_SIZE(sbi_features)) + ret = sbi_features[fid]; + break; default: - ret = -SBI_ENOSYS; + print_sbi_trap(eid); + printk(BIOS_EMERG, "SBI: %lx: ENOSYS\n", fid); + sbiret = -SBI_ENOSYS; break; } - tf->gpr[10] = ret; - write_csr(mepc, read_csr(mepc) + 4); + tf->gpr[10] = sbiret; + tf->gpr[11] = ret; + + write_csr(mepc, retpc); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f Gerrit-Change-Number: 81294 Gerrit-PatchSet: 13 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya>: Remove blank lines before '}' and after '{'
by Eric Lai (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Dinesh Gehlot, Elyes Haouas, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81467?usp=email ) Change subject: mb/google/brya>: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81467?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2729655b16e660fd217c750df3d7817283fb441d Gerrit-Change-Number: 81467 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 25 Mar 2024 02:08:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Shuo Liu (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/coreboot/+/81312/comment/dd8b9b5d_ee3c577b : PS16, Line 192: #if CONFIG(SOC_INTEL_HAS_CXL) > This wasn't necessary before, is it now? The original form (as below), cannot get compilation pass after create_cxl_domains is changed to a static function (create_cxl_domains is defined only at #if CONFIG(SOC_INTEL_HAS_CXL)), if (CONFIG(SOC_INTEL_HAS_CXL) && is_iio_cxl_stack_res(sr)) create_cxl_domains() It look like the compiler cannot handle the branch optimization well in this case. Any opinions? -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 16 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 01:14:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: volteer: Return MCACHE_SIZE to its old value if using vboot
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Nick Vaccaro. Hello Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81512?usp=email to look at the new patch set (#3). Change subject: volteer: Return MCACHE_SIZE to its old value if using vboot ...................................................................... volteer: Return MCACHE_SIZE to its old value if using vboot Existing volteer systems are shipped and update through versions with mcache set to 0x2000. Set it to the same value when creating hybrid images Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81512/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Gerrit-Change-Number: 81512 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: volteer: Return MCACHE_SIZE to its old value if using vboot.
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Nick Vaccaro. Hello Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81512?usp=email to look at the new patch set (#2). Change subject: volteer: Return MCACHE_SIZE to its old value if using vboot. ...................................................................... volteer: Return MCACHE_SIZE to its old value if using vboot. Existing volteer systems are shipped and update through versions with mcache set to 0x2000. Set it to the same value when creating hybrid images Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81512/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Gerrit-Change-Number: 81512 Gerrit-PatchSet: 2 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: volteer: Return MCACHE_SIZE to its old value if using vboot.
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81512?usp=email ) Change subject: volteer: Return MCACHE_SIZE to its old value if using vboot. ...................................................................... volteer: Return MCACHE_SIZE to its old value if using vboot. Existing volteer systems are shipped and update through versions with mcache set to 0x2000. Set it in the code to the same value rather than requiring keeping a patch for updates. Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81512/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 0ab6ee0..8a5676b 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -246,4 +246,8 @@ config USE_PM_ACPI_TIMER default n +config CBFS_MCACHE_SIZE + hex + default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK + endif # BOARD_GOOGLE_BASEBOARD_VOLTEER -- To view, visit https://review.coreboot.org/c/coreboot/+/81512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Gerrit-Change-Number: 81512 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Disable NULL breakpoint at the end of bootblock
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Vladimir Serbinenko. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81506?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Disable NULL breakpoint at the end of bootblock ...................................................................... Disable NULL breakpoint at the end of bootblock If stage is older then it will not be able to correctly disable it when needed. New stages will reenable breakpoint early Change-Id: I6d83dfd8c84ccdd97c1899f206519ada91c990d5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/lib/prog_loaders.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81506/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d83dfd8c84ccdd97c1899f206519ada91c990d5 Gerrit-Change-Number: 81506 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: reboot_to_cros: Add a tool to reboot into ChromeOS in hybrid config
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Vladimir Serbinenko has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81511?usp=email ) Change subject: reboot_to_cros: Add a tool to reboot into ChromeOS in hybrid config ...................................................................... reboot_to_cros: Add a tool to reboot into ChromeOS in hybrid config Change-Id: I9b72d3ab380c70fab336b1cd989c70a83964ccd2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- A util/reboot_to_cros/reboot_to_cros.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81511/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b72d3ab380c70fab336b1cd989c70a83964ccd2 Gerrit-Change-Number: 81511 Gerrit-PatchSet: 2 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Clear spurious recovery request
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Julius Werner, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81509?usp=email to look at the new patch set (#2). Change subject: Clear spurious recovery request ...................................................................... Clear spurious recovery request Some recovery requests are spurious. Clear them and follow RW path regardless Change-Id: I6ba7c954e6c51ef97abc2ff8e2826a95ff6b0532 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/81509/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ba7c954e6c51ef97abc2ff8e2826a95ff6b0532 Gerrit-Change-Number: 81509 Gerrit-PatchSet: 2 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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