coreboot-gerrit March 2024

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[S] Change in coreboot[main]: Support smmstore in RW_LEGACY
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81507?usp=email ) Change subject: Support smmstore in RW_LEGACY ...................................................................... Support smmstore in RW_LEGACY When creating hybrid image with dual-boot we can't add a new fmap for smmstore. Use a file in RW_LEGACY instead Change-Id: I86a617782f187adcce4429ea41ac40a9df58d6d3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/drivers/smmstore/store.c 1 file changed, 26 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/81507/1 diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index bc3dcdc..e7b8b48 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -8,16 +8,21 @@ #include <console/console.h> #include <smmstore.h> #include <types.h> +#include <commonlib/bsd/cbfs_private.h> #define SMMSTORE_REGION "SMMSTORE" +#ifdef FMAP_SECTION_SMMSTORE_START + _Static_assert(IS_ALIGNED(FMAP_SECTION_SMMSTORE_START, SMM_BLOCK_SIZE), "SMMSTORE FMAP region not aligned to 64K"); _Static_assert(SMM_BLOCK_SIZE <= FMAP_SECTION_SMMSTORE_SIZE, "SMMSTORE FMAP region must be at least 64K"); +#endif + /* * The region format is still not finalized, but so far it looks like this: * ( @@ -42,14 +47,26 @@ static enum cb_err lookup_store_region(struct region *region) { - if (fmap_locate_area(SMMSTORE_REGION, region)) { - printk(BIOS_WARNING, - "smm store: Unable to find SMM store FMAP region '%s'\n", - SMMSTORE_REGION); - return CB_ERR; + struct region rw_legacy; + struct region_device rw_legacy_rdev; + union cbfs_mdata mdata; + size_t data_offset; + + if (fmap_locate_area(SMMSTORE_REGION, region) == 0) + return CB_SUCCESS; + + if (fmap_locate_area("RW_LEGACY", &rw_legacy) == 0 + && boot_device_ro_subregion(&rw_legacy, &rw_legacy_rdev) == 0 + && cbfs_lookup(&rw_legacy_rdev, "smmstore.bin", &mdata, &data_offset, NULL) == 0) { + region->offset = rw_legacy.offset + data_offset; + region->size = be32toh(mdata.h.len); + return CB_SUCCESS; } - return CB_SUCCESS; + printk(BIOS_WARNING, + "smm store: Unable to find SMM store FMAP region '%s'\n", + SMMSTORE_REGION); + return CB_ERR; } /* @@ -99,7 +116,9 @@ done = 1; - if (fmap_locate_area_as_rdev_rw(SMMSTORE_REGION, &rdev)) { + struct region ar; + + if (lookup_store_region(&ar) || boot_device_rw_subregion(&ar, &rdev)) { printk(BIOS_WARNING, "smm store: Unable to find SMM store FMAP region '%s'\n", SMMSTORE_REGION); -- To view, visit https://review.coreboot.org/c/coreboot/+/81507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86a617782f187adcce4429ea41ac40a9df58d6d3 Gerrit-Change-Number: 81507 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Disable NULL breakpoint at the end of bootblock
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81506?usp=email ) Change subject: Disable NULL breakpoint at the end of bootblock ...................................................................... Disable NULL breakpoint at the end of bootblock If stage is older then it will not be able to correctly disable it when needed. New stages will reenable breakpoint early Change-Id: I6d83dfd8c84ccdd97c1899f206519ada91c990d5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/lib/prog_loaders.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81506/1 diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index b2abbff..ee74c40 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -14,6 +14,9 @@ #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> +#if CONFIG(DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) +#include <arch/null_breakpoint.h> +#endif void run_romstage(void) { @@ -39,6 +42,12 @@ goto fail; } +#if CONFIG(DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) + /* When going from bootblock disable null breakpoint as romstage + might not have this enabled or be too old. */ + null_breakpoint_disable(); +#endif + timestamp_add_now(TS_COPYROM_END); console_time_report(); -- To view, visit https://review.coreboot.org/c/coreboot/+/81506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d83dfd8c84ccdd97c1899f206519ada91c990d5 Gerrit-Change-Number: 81506 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: Support loading legacy stage
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Julius Werner. Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81505?usp=email ) Change subject: Support loading legacy stage ...................................................................... Support loading legacy stage This allows to create hybrid images that boot old signed stage image in one of RW_A/RW_B and a newer RO with newer behaviour. This allows to have dual-boot between stock ChromeOS and custom coreboot Change-Id: I4ae29a6227235c86f9f846986c18b361c3b3c78d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h M src/lib/cbfs.c 2 files changed, 77 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/81505/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index b6a7baa..4109f1c 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -178,6 +178,17 @@ /* Following are component sub-headers for the "standard" component types */ +/** This is the sub-header for legacy stage components. Stages are + loaded by coreboot during the normal boot process */ + +struct cbfs_legacy_stage { + uint32_t compression; /** Compression type */ + uint64_t entry; /** entry point */ + uint64_t load; /** Where to load in memory */ + uint32_t len; /** length of data to load */ + uint32_t memlen; /** total length of object in memory */ +} __packed; + /** this is the sub-header for payload components. Payloads are loaded by coreboot at the end of the boot process */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 03624bf..19df07f 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -206,11 +206,11 @@ return false; } -static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *buffer, - size_t buffer_size, uint32_t compression, - const union cbfs_mdata *mdata, bool skip_verification) + +static size_t cbfs_load_and_decompress_offset(const struct region_device *rdev, void *buffer, + size_t buffer_size, uint32_t compression, + const union cbfs_mdata *mdata, bool skip_verification, size_t in_offset, size_t in_size) { - size_t in_size = region_device_sz(rdev); size_t out_size = 0; void *map; @@ -228,7 +228,7 @@ case CBFS_COMPRESS_NONE: if (buffer_size < in_size) return 0; - if (rdev_readat(rdev, buffer, 0, in_size) != in_size) + if (rdev_readat(rdev, buffer, in_offset, in_size) != in_size) return 0; if (cbfs_file_hash_mismatch(buffer, in_size, mdata, skip_verification)) return 0; @@ -240,7 +240,7 @@ /* cbfs_prog_stage_load() takes care of in-place LZ4 decompression by setting up the rdev to be in memory. */ - map = rdev_mmap_full(rdev); + map = rdev_mmap(rdev, in_offset, in_size); if (map == NULL) return 0; @@ -257,7 +257,7 @@ case CBFS_COMPRESS_LZMA: if (!cbfs_lzma_enabled()) return 0; - map = rdev_mmap_full(rdev); + map = rdev_mmap(rdev, in_offset, in_size); if (map == NULL) return 0; @@ -277,6 +277,13 @@ } } +static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *buffer, + size_t buffer_size, uint32_t compression, + const union cbfs_mdata *mdata, bool skip_verification) +{ + return cbfs_load_and_decompress_offset(rdev, buffer, buffer_size, compression, mdata, skip_verification, 0, region_device_sz(rdev)); +} + struct cbfs_preload_context { struct region_device rdev; struct thread_handle handle; @@ -560,39 +567,72 @@ if ((err = _cbfs_boot_lookup(prog_name(pstage), false, &mdata, &rdev))) return err; - assert(be32toh(mdata.h.type) == CBFS_TYPE_STAGE); - pstage->cbfs_type = CBFS_TYPE_STAGE; + uint32_t stage_type = be32toh(mdata.h.type); + assert(stage_type == CBFS_TYPE_STAGE || stage_type == CBFS_TYPE_LEGACY_STAGE); + pstage->cbfs_type = stage_type; enum cbfs_compression compression = CBFS_COMPRESS_NONE; - const struct cbfs_file_attr_compression *cattr = cbfs_find_attr(&mdata, - CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*cattr)); - if (cattr) - compression = be32toh(cattr->compression); + size_t foffset = 0; + size_t fsize = region_device_sz(&rdev); + size_t memsize; + uint8_t *load; - const struct cbfs_file_attr_stageheader *sattr = cbfs_find_attr(&mdata, - CBFS_FILE_ATTR_TAG_STAGEHEADER, sizeof(*sattr)); - if (!sattr) - return CB_ERR; - prog_set_area(pstage, (void *)(uintptr_t)be64toh(sattr->loadaddr), - be32toh(sattr->memlen)); - prog_set_entry(pstage, prog_start(pstage) + + if (stage_type == CBFS_TYPE_LEGACY_STAGE) { + struct cbfs_legacy_stage legacy_stage; + void *entry; + if (rdev_readat(&rdev, &legacy_stage, 0, sizeof(legacy_stage)) != sizeof(legacy_stage)) + return CB_CBFS_IO; + + fsize -= sizeof(legacy_stage); + foffset += sizeof(legacy_stage); + + /* cbfs_stage fields are written in little endian despite the other + cbfs data types being encoded in big endian. */ + compression = le32toh(legacy_stage.compression); + entry = (void *)(uintptr_t)le64toh(legacy_stage.entry); + load = (void *)(uintptr_t)le64toh(legacy_stage.load); + memsize = le32toh(legacy_stage.memlen); + + assert(fsize == le32toh(legacy_stage.len)); + prog_set_area(pstage, load, memsize); + prog_set_entry(pstage, entry, NULL); + } else { + const struct cbfs_file_attr_compression *cattr = cbfs_find_attr(&mdata, + CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*cattr)); + if (cattr) + compression = be32toh(cattr->compression); + + const struct cbfs_file_attr_stageheader *sattr = cbfs_find_attr(&mdata, + CBFS_FILE_ATTR_TAG_STAGEHEADER, sizeof(*sattr)); + if (!sattr) + return CB_ERR; + prog_set_area(pstage, (void *)(uintptr_t)be64toh(sattr->loadaddr), + be32toh(sattr->memlen)); + prog_set_entry(pstage, prog_start(pstage) + be32toh(sattr->entry_offset), NULL); + load = prog_start(pstage); + memsize = prog_size(pstage); + } /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { - void *mapping = rdev_mmap_full(&rdev); + void *mapping = rdev_mmap(&rdev, foffset, fsize); rdev_munmap(&rdev, mapping); if (cbfs_file_hash_mismatch(mapping, region_device_sz(&rdev), &mdata, false)) return CB_CBFS_HASH_MISMATCH; - if (mapping == prog_start(pstage)) + if (mapping == load) { + printk(BIOS_DEBUG, "Running stage in-place at %p, entry=%p\n", mapping, prog_entry(pstage)); return CB_SUCCESS; + } } /* LZ4 stages can be decompressed in-place to save mapping scratch space. Load the compressed data to the end of the buffer and point &rdev to that memory location. */ if (cbfs_lz4_enabled() && compression == CBFS_COMPRESS_LZ4) { + assert(stage_type == CBFS_TYPE_STAGE); + size_t in_size = region_device_sz(&rdev); void *compr_start = prog_start(pstage) + prog_size(pstage) - in_size; if (rdev_readat(&rdev, compr_start, 0, in_size) != in_size) @@ -600,16 +640,15 @@ rdev_chain_mem(&rdev, compr_start, in_size); } - size_t fsize = cbfs_load_and_decompress(&rdev, prog_start(pstage), prog_size(pstage), - compression, &mdata, false); + fsize = cbfs_load_and_decompress_offset(&rdev, load, memsize, + compression, &mdata, false, foffset, fsize); if (!fsize) return CB_ERR; /* Clear area not covered by file. */ - memset(prog_start(pstage) + fsize, 0, prog_size(pstage) - fsize); + memset(load + fsize, 0, memsize - fsize); - prog_segment_loaded((uintptr_t)prog_start(pstage), prog_size(pstage), - SEG_FINAL); + prog_segment_loaded((uintptr_t)load, memsize, SEG_FINAL); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae29a6227235c86f9f846986c18b361c3b3c78d Gerrit-Change-Number: 81505 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: cbfstool: Add printing of legacy stage type
by Vladimir Serbinenko (Code Review) 24 Mar '24

24 Mar '24

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81504?usp=email ) Change subject: cbfstool: Add printing of legacy stage type ...................................................................... cbfstool: Add printing of legacy stage type This is useful for listing older images. Change-Id: I588028d4327f59538f7c9920b671458fc631cb4c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M util/cbfstool/cbfs.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/81504/1 diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index eca7168..3336e08 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -31,6 +31,7 @@ static struct typedesc_t filetypes[] unused = { {CBFS_TYPE_BOOTBLOCK, "bootblock"}, {CBFS_TYPE_CBFSHEADER, "cbfs header"}, + {CBFS_TYPE_LEGACY_STAGE, "legacy stage"}, {CBFS_TYPE_STAGE, "stage"}, {CBFS_TYPE_SELF, "simple elf"}, {CBFS_TYPE_FIT_PAYLOAD, "fit_payload"}, -- To view, visit https://review.coreboot.org/c/coreboot/+/81504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I588028d4327f59538f7c9920b671458fc631cb4c Gerrit-Change-Number: 81504 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: superio/ite: Add special fan vectors and further options
by Joel Linn (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Matt DeVillier, Nico Huber. Joel Linn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81426?usp=email ) Change subject: superio/ite: Add special fan vectors and further options ...................................................................... Patch Set 4: (1 comment) File src/superio/ite/common/env_ctrl.c: https://review.coreboot.org/c/coreboot/+/81426/comment/e2bdf4c4_53a905ed : PS1, Line 369: #endif > I guess the original intention was to keep the configuration struct clean […] A new C file would still require the code to be called from somewhere and thus yield similar "problems" as we were discussing already, wouldn't it? -- To view, visit https://review.coreboot.org/c/coreboot/+/81426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Gerrit-Change-Number: 81426 Gerrit-PatchSet: 4 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sun, 24 Mar 2024 23:26:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms
by Nico Huber (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81219?usp=email ) Change subject: soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Gerrit-Change-Number: 81219 Gerrit-PatchSet: 13 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 24 Mar 2024 23:04:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Nico Huber (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... Patch Set 16: Code-Review+1 (1 comment) File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/coreboot/+/81312/comment/38b4dd32_1a1ca8bb : PS16, Line 192: #if CONFIG(SOC_INTEL_HAS_CXL) This wasn't necessary before, is it now? -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 16 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 24 Mar 2024 22:59:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: doc/getting_started: Update embedded-table examples
by Nico Huber (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81503?usp=email ) Change subject: doc/getting_started: Update embedded-table examples ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > *each cell is one row and one column Ok, so then let's keep it simple and keep suggesting to use rST tables? -- To view, visit https://review.coreboot.org/c/coreboot/+/81503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b0d0b029fd527e0e18c71371806cd248ea0ecdf Gerrit-Change-Number: 81503 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 24 Mar 2024 22:53:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: doc/getting_started: Update embedded-table examples
by Nico Huber (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Nico Huber. Hello Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81503?usp=email to look at the new patch set (#2). Change subject: doc/getting_started: Update embedded-table examples ...................................................................... doc/getting_started: Update embedded-table examples Since commit 35599f9a6671 (Docs: Replace Recommonmark with MyST Parser), `{eval-rst}' is used instead of `eval_rst' for embedded rST. Change-Id: I1b0d0b029fd527e0e18c71371806cd248ea0ecdf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/81503/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b0d0b029fd527e0e18c71371806cd248ea0ecdf Gerrit-Change-Number: 81503 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Move domain resources adding to their creation
by Nico Huber (Code Review) 24 Mar '24

24 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81435?usp=email ) Change subject: soc/intel/xeon_sp: Move domain resources adding to their creation ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81435/comment/e79fc0e4_27c935f2 : PS2, Line 202: add_domain_resources(domain); If this is just called at the very end, you could also call it after this function (would save the whole function-pointer parameter). File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/coreboot/+/81435/comment/167062cd_fbc97004 : PS2, Line 30: static void iio_pci_domain_add_resources(struct device *dev) My thought was to pass the stack res here, so we don't have to look it up again. -- To view, visit https://review.coreboot.org/c/coreboot/+/81435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba58dc9ac1d2e7d07004ee2bb0cc76b273d37e99 Gerrit-Change-Number: 81435 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 24 Mar 2024 22:52:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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