coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: Disable NULL breakpoint at the end of bootblock
by Arthur Heymans (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Vladimir Serbinenko. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81506?usp=email ) Change subject: Disable NULL breakpoint at the end of bootblock ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81506/comment/7b6e25c7_ed55a645 : PS3, Line 9: If stage is older then it will not be able to correctly disable it when : needed. New stages will reenable breakpoint early > It happens in my case. With standard ChromeOS the RW parts are updated and signed by Google and entire OS update fails if the RW part can't be updated. RO is never checked or updated. So after unlock we can replace it with our code as long as it's compatible with the old ABI used by RW part That's a use case that's generally not supported upstream: other environment things like linker scripts for CAR usage are not guaranteed to match. Why not set DEBUG_NULL_DEREF_BREAKPOINTS to 'n' when building that RO? -- To view, visit https://review.coreboot.org/c/coreboot/+/81506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d83dfd8c84ccdd97c1899f206519ada91c990d5 Gerrit-Change-Number: 81506 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 10:40:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add soc_acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: acpi: Add soc_acpigen_write_OSC_pci_domain ...................................................................... Patch Set 8: (5 comments) Patchset: PS8: Thanks for nice suggestions, updated! File src/acpi/acpigen_pci.c: https://review.coreboot.org/c/coreboot/+/81375/comment/ed85d62d_50461c29 : PS8, Line 164: > `OSC_RET_UNRECOGNIZED_REV` is unused and check for Arg1 is missing. Done https://review.coreboot.org/c/coreboot/+/81375/comment/f0c501cd_c809b081 : PS8, Line 229: RETE > RETE is always 0 here, no need to or OSC_RET_FAILURE with it. […] Done https://review.coreboot.org/c/coreboot/+/81375/comment/3fdc6125_a8b72add : PS8, Line 291: acpigen_write_to_integer_from_namestring > RETE is always 0 here, no need to or OSC_RET_FAILURE with it. […] Done https://review.coreboot.org/c/coreboot/+/81375/comment/35e1f6af_ff553313 : PS8, Line 328: acpigen_emit_byte > You can emit the namestring directly without using a local variable. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 10:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add soc_acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Tim Wawrzynczak. Hello Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81375?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: acpi: Add soc_acpigen_write_OSC_pci_domain ...................................................................... acpi: Add soc_acpigen_write_OSC_pci_domain Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/gnr/soc_acpi.c 3 files changed, 312 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81375/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/msi: Remove blank lines before '}' and after '{'
by Michał Kopeć (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Elyes Haouas, Michał Żygowski. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81485?usp=email ) Change subject: mb/msi: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81485?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a678b433e3e1a492e2a8e679caf75f4741317cb Gerrit-Change-Number: 81485 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 25 Mar 2024 09:48:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Move domain resources adding to their creation
by Nico Huber (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81435?usp=email ) Change subject: soc/intel/xeon_sp: Move domain resources adding to their creation ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81435/comment/ccbc3d1e_e5d84744 : PS3, Line 9: Domain Sorry, the whole thing was my idea. Some thoughts: * Avoids the need to look up the HOB again and thereby avoids the need to work around the devicetree by reconstructing information via `xeon_domain_path`. * Reduces the complexity. * Aligns with other cases where resources are predetermined and not chosen by coreboot's runtime, e.g. via static devicetree. > I don't see a good reason to break the device_operations API and here's no reason given. IMO, the device_operations API is designed for hardware. I think I mentioned elsewhere that reading the resources from hardware might also be a (lean?) solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/81435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba58dc9ac1d2e7d07004ee2bb0cc76b273d37e99 Gerrit-Change-Number: 81435 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 09:25:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes
by Nico Huber (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81312?usp=email ) Change subject: soc/intel/xeon_sp: Unshare Xeon-SP chip common codes ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/coreboot/+/81312/comment/45b32864_790d7823 : PS16, Line 192: #if CONFIG(SOC_INTEL_HAS_CXL) > The original form (as below), cannot get compilation pass after create_cxl_domains is changed to a s […] You would have to declare it, e.g. in line 185: ``` #else void create_cxl_domains(const union xeon_domain_path dp, struct bus *bus, const STACK_RES *sr, const size_t pci_segment_group); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/81312?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab6acaa5e5c090c8d821bd7c2d3e0e0ad7486bdc Gerrit-Change-Number: 81312 Gerrit-PatchSet: 16 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 09:19:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Disable NULL breakpoint at the end of bootblock
by Vladimir Serbinenko (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans. Vladimir Serbinenko has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81506?usp=email ) Change subject: Disable NULL breakpoint at the end of bootblock ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81506/comment/721eb4da_1f3af00d : PS3, Line 9: If stage is older then it will not be able to correctly disable it when : needed. New stages will reenable breakpoint early > It's a bit strange to have a bootblock that is newer than the following stages? It happens in my case. With standard ChromeOS the RW parts are updated and signed by Google and entire OS update fails if the RW part can't be updated. RO is never checked or updated. So after unlock we can replace it with our code as long as it's compatible with the old ABI used by RW part -- To view, visit https://review.coreboot.org/c/coreboot/+/81506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d83dfd8c84ccdd97c1899f206519ada91c990d5 Gerrit-Change-Number: 81506 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 25 Mar 2024 09:13:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: vc/intel/fsp/mtl: Update header files from 3471_91 to 3471_92
by Name of user not set (Code Review) 25 Mar '24

25 Mar '24

srinivas.kulkarni(a)intel.com has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81231?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3471_91 to 3471_92 ...................................................................... Abandoned We do not need to upstream this and hence abandoning the change -- To view, visit https://review.coreboot.org/c/coreboot/+/81231?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19bd52ebdb14af5b768d996a4586eddef67e7033 Gerrit-Change-Number: 81231 Gerrit-PatchSet: 3 Gerrit-Owner: srinivas.kulkarni(a)intel.com Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Henry Barnor <hbarnor(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.corp-partner.google.com> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: libpayload: Include commonlib/helpers.h in libpayload.h for GPL builds
by Yu-Ping Wu (Code Review) 25 Mar '24

25 Mar '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81289?usp=email ) Change subject: libpayload: Include commonlib/helpers.h in libpayload.h for GPL builds ...................................................................... libpayload: Include commonlib/helpers.h in libpayload.h for GPL builds This patch makes the GPL-restricted commonlib helpers available in libpayload when CONFIG_LP_GPL is selected, as a convenience to GPL payloads that use them a lot. Cq-Depend: chromium:5375721 Change-Id: I844c6e700c4c0d557f97da94fa3aa2e868edd756 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81289 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M payloads/libpayload/include/libpayload.h 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index c6d2fc6..09bd4be 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -45,9 +45,13 @@ #include <stdbool.h> #include <libpayload-config.h> #include <cbgfx.h> +#if CONFIG(LP_GPL) +#include <commonlib/helpers.h> +#else +#include <commonlib/bsd/helpers.h> +#endif #include <commonlib/bsd/elog.h> #include <commonlib/bsd/fmap_serialized.h> -#include <commonlib/bsd/helpers.h> #include <commonlib/bsd/ipchksum.h> #include <commonlib/bsd/mem_chip_info.h> #include <ctype.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/81289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I844c6e700c4c0d557f97da94fa3aa2e868edd756 Gerrit-Change-Number: 81289 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: libpayload: Include commonlib/helpers.h in libpayload.h for GPL builds
by Yu-Ping Wu (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81289?usp=email ) Change subject: libpayload: Include commonlib/helpers.h in libpayload.h for GPL builds ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I844c6e700c4c0d557f97da94fa3aa2e868edd756 Gerrit-Change-Number: 81289 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 25 Mar 2024 08:13:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2024