coreboot-gerrit March 2024

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[M] Change in coreboot[main]: arch/riscv: linuxcheck framework which runs from ramstage
by ron minnich (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81367?usp=email to look at the new patch set (#9). Change subject: arch/riscv: linuxcheck framework which runs from ramstage ...................................................................... arch/riscv: linuxcheck framework which runs from ramstage Errors in Linux booting are notoriously hard to debug. This change adds a linuxcheck framework that allows testing of things Linux (and other kernels) needs, without having to debug Linux. If LINUXCHECK is set during menuconfig, the linuxcheck function will be called, in S mode, from the ramstage. That function then runs code, in S mode, that tests coreboot M mode code such as SBI. This is extremely handy: because linuxcheck is built into the ramstage, it allows calling any ramstage function, e.g. printk, if required; at the same time, the function is running in S mode, so it is very easy to test SBI calls, instruction emulation, and so on. Note that, if CONFIG_LINUXCHECK is set, the PMPs should enable RWX permissions (instead of R permissions) on the ramstage. For now, until we get the rest of the debugging done, we unconditionally set the permissions. This is a very powerful approach that could also form the core of an SBI fuzzing suite; unlike the currently proposed one, which is based on the KVM fuzzer, this code would not require a Linux kernel to test. It is very light weight. This is also better than the older linuxcheck payload, since it does not need libpayload or seperate compilation. It reduces the testing of SBI and other trap code to its simplest form, and allows to focus on testing SBI, not fighting build systems and large complex kernels. Change-Id: I7d19147b9df57c63ec7301da243fd5541e9952a7 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk M src/arch/riscv/include/arch/cpu.h A src/arch/riscv/linuxcheck.c M src/arch/riscv/payload.c 5 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81367/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d19147b9df57c63ec7301da243fd5541e9952a7 Gerrit-Change-Number: 81367 Gerrit-PatchSet: 9 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/riscv: Basic illegal instruction handling
by ron minnich (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Philipp Hug. Hello Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81306?usp=email to look at the new patch set (#11). Change subject: arch/riscv: Basic illegal instruction handling ...................................................................... arch/riscv: Basic illegal instruction handling Add a simple illegal instruction handler, designed for lowest overhead as opposed to generality. coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-) So, in general, on future systems, reads will not trap. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 74 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 11 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: arch/riscv: remove misaligned load/store/fetch handling
by ron minnich (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Philipp Hug, ron minnich. Hello Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81416?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: remove misaligned load/store/fetch handling ...................................................................... arch/riscv: remove misaligned load/store/fetch handling Testing on the unmatched shows the code no longer works completely correctly; Linux has taken over the handling of misalignment anyway, because handling it in firmware, with the growing complexity of the ISA and the awkward way in which it has to be handled, is more trouble than its worth. Plus, we don't WANT misalignment handled, magically, in firmware: the cost of getting it wrong is high (as I've spent a month learning); the performance is terrible (350x slowdown; and most toolchains now know to avoid unaligned load/store on RISC-V anyway. But, mostly, if alignment problems exist, *we need to know*, and if they're handled invisibly in firmware, we don't. The problem with invisble handling was shown a while back in the Go toolchain: runtime had a small error, such that many misaligned load/store were happening, and it was not discovered for some time. Had a trap been directed to kernel or user on misalignment, the problem would have been known immediately, not after many months. (The error, btw, was masking the address with 3, not 7, to detect misalignment; an easy mistake!). But, the coreboot code does not work any more any way, and it's not worth fixing. Remove it. Tested by booting Linux to runlevel 1; before, it would hang on an alignment fault, as the alignment code was failing (somewhere). This takes the coreboot SBI code much closer to revival. Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Makefile.mk M src/arch/riscv/include/arch/exception.h D src/arch/riscv/misaligned.c M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 5 files changed, 4 insertions(+), 265 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81416/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81416?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Gerrit-Change-Number: 81416 Gerrit-PatchSet: 5 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain
by Patrick Rudolph (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Shuo Liu, Tim Chu, Tim Wawrzynczak. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: acpi: Add acpigen_write_OSC_pci_domain ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 16:36:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/bootblock.ld: Account for the .data section
by Arthur Heymans (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Jérémy Compostella. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81434?usp=email ) Change subject: arch/x86/bootblock.ld: Account for the .data section ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Good catch, did you it any issue ? I'm not sure. With CB:63419 romstage gets linked into the bootblock. The linker wasn't happy so I tried to narrow it down (it was weirdly complaining about mrc CAR region) (See https://qa.coreboot.org/job/coreboot-gerrit/254403/testReport/junit/(root)/…). As usual linkers are not too great at telling you what is wrong when they fails. This was something I noticed that could be wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/81434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39abe499e5e9edbdacb1697c0a0fc347af3ef9c4 Gerrit-Change-Number: 81434 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 16:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/bootblock.ld: Account for the .data section
by Jérémy Compostella (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Arthur Heymans. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81434?usp=email ) Change subject: arch/x86/bootblock.ld: Account for the .data section ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Good catch, did you it any issue ? -- To view, visit https://review.coreboot.org/c/coreboot/+/81434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39abe499e5e9edbdacb1697c0a0fc347af3ef9c4 Gerrit-Change-Number: 81434 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 25 Mar 2024 16:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/samsung/stumpy: Set initial fan PWM to 30%
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Matt DeVillier has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/81514?usp=email ) Change subject: mb/samsung/stumpy: Set initial fan PWM to 30% ...................................................................... mb/samsung/stumpy: Set initial fan PWM to 30% Recent changes to the ITE 8772F SIO code caused the initial fan PWM to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot stumpy to payload, verify fan noise is negligible. Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/samsung/stumpy/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/81514/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Gerrit-Change-Number: 81514 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/beltino: Set initial fan PWM to 30%
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Matt DeVillier has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81513?usp=email ) Change subject: mb/google/beltino: Set initial fan PWM to 30% ...................................................................... mb/google/beltino: Set initial fan PWM to 30% Recent changes to the ITE 8772F SIO code caused the initial fan PWM to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot google/beltino to payload, verify fan noise is negligible. Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/81513/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81513?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177235d73e051f02b5333cf1d735556382b919f Gerrit-Change-Number: 81513 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/samsung/stumpy: Set initial fan PWM to 30%
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Matt DeVillier has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81514?usp=email ) Change subject: mb/samsung/stumpy: Set initial fan PWM to 30% ...................................................................... mb/samsung/stumpy: Set initial fan PWM to 30% Recent changes to the ITE 8772F SIO code caused the initial fan PMW to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot stumpy to payload, verify fan noise is negligible. Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/samsung/stumpy/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/81514/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Gerrit-Change-Number: 81514 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/samsung/stumpy: Set initial fan PWM to 30%
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81514?usp=email ) Change subject: mb/samsung/stumpy: Set initial fan PWM to 30% ...................................................................... mb/samsung/stumpy: Set initial fan PWM to 30% Recent changes to the ITE 8772F SIO code caused the initial fan PMW to change from 0 to 50%; set it to 30% to reduce fan noise while still providing some temp control before the OS/ACPI takes over. TEST=build/boot stumpy to payload, verify fan noise is negligable. Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/samsung/stumpy/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/81514/1 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 853e519..bc24464 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -91,6 +91,7 @@ register "TMPIN3.mode" = "THERMAL_PECI" # Enable FAN3 register "FAN3.mode" = "FAN_SMART_SOFTWARE" + register "FAN3.smart.pwm_start" = "30" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I287e46202ee1c112d1da63c0d8b7889958e3807e Gerrit-Change-Number: 81514 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024