coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: superio/ite: Add special fan vectors and further options
by Joel Linn (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Joel Linn, Nico Huber. Hello Matt DeVillier, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81426?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: superio/ite: Add special fan vectors and further options ...................................................................... superio/ite: Add special fan vectors and further options A number of ITE SIOs support "special fan control vectors", which effectively allow non-linear fan speed control. This is for example used by the vendor firmware of the "HP Pro 3500 Series". The 3VSBSW# signal can now also be disabled again which is necessary to power components down properly in SMM when entering S5. A function to disable the PME# output was added as well. Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Signed-off-by: Joel Linn <jl(a)conductive.de> --- M src/superio/ite/Makefile.mk M src/superio/ite/common/Kconfig M src/superio/ite/common/early_serial.c M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h M src/superio/ite/common/ite.h M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8772f/Kconfig 9 files changed, 118 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/81426/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Gerrit-Change-Number: 81426 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: superio/ite: Unify it8772f with common code
by Joel Linn (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Joel Linn, Michał Żygowski, MrChromebox, Nico Huber, Piotr Król. Hello Matt DeVillier, Michał Żygowski, MrChromebox, Nico Huber, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81310?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: superio/ite: Unify it8772f with common code ...................................................................... superio/ite: Unify it8772f with common code The it8772f is now configured by the much better common code that is used for other chips in the family as well. This mainly concerns the EC, the GPIO functionality was not moved to common as it currently lacks a sane abstraction in any codebase. The datasheets of the it8772e(f) and it8728f (for reference) were studied and verified against the common code, adding exceptions where needed. Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Signed-off-by: Joel Linn <jl(a)conductive.de> --- M src/mainboard/google/beltino/bootblock.c M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/beltino/onboard.h M src/mainboard/google/jecht/bootblock.c M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/jecht/onboard.h M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/samsung/stumpy/early_init.c M src/mainboard/samsung/stumpy/smihandler.c M src/superio/ite/common/early_serial.c M src/superio/ite/common/ite.h M src/superio/ite/it8772f/chip.h M src/superio/ite/it8772f/early_init.c M src/superio/ite/it8772f/it8772f.h M src/superio/ite/it8772f/superio.c 16 files changed, 61 insertions(+), 326 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81310/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Gerrit-Change-Number: 81310 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Attention: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: arch/riscv: remove misaligned load/store/fetch handling
by ron minnich (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81416?usp=email ) Change subject: arch/riscv: remove misaligned load/store/fetch handling ...................................................................... Patch Set 7: (1 comment) File src/arch/riscv/trap_handler.c: https://review.coreboot.org/c/coreboot/+/81416/comment/60eeed9e_4ed6bb6e : PS4, Line 140: case CAUSE_ILLEGAL_INSTRUCTION: > damn, that's weird. ok, will fix. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81416?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Gerrit-Change-Number: 81416 Gerrit-PatchSet: 7 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 23:18:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: arch/riscv: remove misaligned load/store/fetch handling
by ron minnich (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81416?usp=email ) Change subject: arch/riscv: remove misaligned load/store/fetch handling ...................................................................... Patch Set 7: (2 comments) Patchset: PS7: long story, had to do this on a cloud machine yesterday and it got out of sunc. File src/arch/riscv/trap_handler.c: https://review.coreboot.org/c/coreboot/+/81416/comment/282ccee1_60d484e5 : PS4, Line 140: case CAUSE_ILLEGAL_INSTRUCTION: > Now you added it to the commit-msg, but you moved it back to its original state? damn, that's weird. ok, will fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/81416?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Gerrit-Change-Number: 81416 Gerrit-PatchSet: 7 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 23:18:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: arch/riscv: remove misaligned load/store/fetch handling
by ron minnich (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Philipp Hug, ron minnich. Hello Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81416?usp=email to look at the new patch set (#7). Change subject: arch/riscv: remove misaligned load/store/fetch handling ...................................................................... arch/riscv: remove misaligned load/store/fetch handling Testing on the unmatched shows the code no longer works completely correctly; Linux has taken over the handling of misalignment anyway, because handling it in firmware, with the growing complexity of the ISA and the awkward way in which it has to be handled, is more trouble than its worth. Plus, we don't WANT misalignment handled, magically, in firmware: the cost of getting it wrong is high (as I've spent a month learning); the performance is terrible (350x slowdown; and most toolchains now know to avoid unaligned load/store on RISC-V anyway. But, mostly, if alignment problems exist, *we need to know*, and if they're handled invisibly in firmware, we don't. The problem with invisble handling was shown a while back in the Go toolchain: runtime had a small error, such that many misaligned load/store were happening, and it was not discovered for some time. Had a trap been directed to kernel or user on misalignment, the problem would have been known immediately, not after many months. (The error, btw, was masking the address with 3, not 7, to detect misalignment; an easy mistake!). But, the coreboot code does not work any more any way, and it's not worth fixing. Remove it. Tested by booting Linux to runlevel 1; before, it would hang on an alignment fault, as the alignment code was failing (somewhere). This takes the coreboot SBI code much closer to revival. Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Makefile.mk M src/arch/riscv/include/arch/exception.h D src/arch/riscv/misaligned.c M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 5 files changed, 4 insertions(+), 265 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81416/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81416?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Gerrit-Change-Number: 81416 Gerrit-PatchSet: 7 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: security/vboot: extract secdata_tpm{1,2}.c
by Julius Werner (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Sergii Dmytruk, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81415?usp=email ) Change subject: security/vboot: extract secdata_tpm{1,2}.c ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81415?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0090b748d7d3b2d76a941b87b5885682fd81c4fc Gerrit-Change-Number: 81415 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 22:42:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: volteer: Return MCACHE_SIZE to its old value if using vboot
by Vladimir Serbinenko (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Nick Vaccaro, Vladimir Serbinenko. Hello Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81512?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: volteer: Return MCACHE_SIZE to its old value if using vboot ...................................................................... volteer: Return MCACHE_SIZE to its old value if using vboot Existing volteer systems are shipped and update through versions with mcache set to 0x2000. Set it to the same value when creating hybrid images Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81512/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Gerrit-Change-Number: 81512 Gerrit-PatchSet: 6 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Clear spurious recovery request
by Vladimir Serbinenko (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Julius Werner, Vladimir Serbinenko, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81509?usp=email to look at the new patch set (#4). Change subject: Clear spurious recovery request ...................................................................... Clear spurious recovery request Some recovery requests are spurious. Clear them and follow RW path regardless Change-Id: I6ba7c954e6c51ef97abc2ff8e2826a95ff6b0532 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/81509/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ba7c954e6c51ef97abc2ff8e2826a95ff6b0532 Gerrit-Change-Number: 81509 Gerrit-PatchSet: 4 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: Support for creating hybrid vboot images
by Vladimir Serbinenko (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Julius Werner, Nick Vaccaro, Vladimir Serbinenko, Yu-Ping Wu. Hello Julius Werner, Nick Vaccaro, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81508?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Support for creating hybrid vboot images ...................................................................... Support for creating hybrid vboot images This allows creating an image where RO is triggered by default with normal RW secrets locked out. On a signal in CMOS, clear the signal and follow normal RW_A/RW_B path. This allows dual-boot between stock ChromeOS and an alternative payload while keeping compatibility with ChromeOS updates. Change-Id: I9b26c332f5bf6befd62b5930b19d1b20e76261e7 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/mainboard/google/volteer/Kconfig M src/security/vboot/Kconfig M src/security/vboot/misc.h M src/security/vboot/vboot_common.h M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c M src/soc/intel/common/block/cse/cse_eop.c 8 files changed, 113 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/81508/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b26c332f5bf6befd62b5930b19d1b20e76261e7 Gerrit-Change-Number: 81508 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: volteer: Return MCACHE_SIZE to its old value if using hybrid vboot
by Vladimir Serbinenko (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Nick Vaccaro. Hello Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81512?usp=email to look at the new patch set (#5). Change subject: volteer: Return MCACHE_SIZE to its old value if using hybrid vboot ...................................................................... volteer: Return MCACHE_SIZE to its old value if using hybrid vboot Existing volteer systems are shipped and update through versions with mcache set to 0x2000. Set it to the same value when creating hybrid images Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81512/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Gerrit-Change-Number: 81512 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024