coreboot-gerrit March 2024

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[M] Change in coreboot[main]: superio/ite: Add special fan vectors and further options
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Joel Linn, Nico Huber. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81426?usp=email ) Change subject: superio/ite: Add special fan vectors and further options ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81426/comment/0b50c89c_e591d790 : PS5, Line 12: : The 3VSBSW# signal can now also be disabled again which is necessary to : power components down properly in SMM when entering S5. : : A function to disable the PME# output was added as well. I think these two can be be individual commits, separate from the fan vector control -- To view, visit https://review.coreboot.org/c/coreboot/+/81426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Gerrit-Change-Number: 81426 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Tue, 26 Mar 2024 01:09:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: superio/ite: Add special fan vectors and further options
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Joel Linn, Nico Huber. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81426?usp=email ) Change subject: superio/ite: Add special fan vectors and further options ...................................................................... Patch Set 5: (2 comments) File src/superio/ite/common/Kconfig: https://review.coreboot.org/c/coreboot/+/81426/comment/c2da8221_c46de9d2 : PS5, Line 61: config SUPERIO_ITE_ENV_CTRL_FAN_VECTOR_RANGED does this need `depends on SUPERIO_ITE_ENV_CTRL_FAN_VECTOR` ? File src/superio/ite/common/env_ctrl.c: https://review.coreboot.org/c/coreboot/+/81426/comment/0682beeb_083f7907 : PS1, Line 369: #endif > I implemented Matt's suggestion. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Gerrit-Change-Number: 81426 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Tue, 26 Mar 2024 01:08:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: superio/ite: Fix warnings, add full-speed config option
by Matt DeVillier (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Joel Linn, Nico Huber. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81516?usp=email ) Change subject: superio/ite: Fix warnings, add full-speed config option ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81516/comment/02194733_bfe72941 : PS1, Line 7: Fix warnings, add full-speed config option these look like they can be easily split into 2 separate commits -- To view, visit https://review.coreboot.org/c/coreboot/+/81516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155 Gerrit-Change-Number: 81516 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Tue, 26 Mar 2024 01:01:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Support for creating hybrid vboot images
by Julius Werner (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Nick Vaccaro, Vladimir Serbinenko, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81508?usp=email ) Change subject: Support for creating hybrid vboot images ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: I'm honestly not really sure what you're trying to do here anyway. Can you describe your high-level goal in more detail? It looks like you're adding a separate CMOS field that can control whether coreboot boots in recovery mode (from the RO partition) or as normal from the RW partition. So I'm assuming that you install the normal ChromeOS coreboot and payload in the RW slot and your own alternative OS firmware and payload in the RO slot? Or the other way round? But then I don't really understand why you're doing all this work to try to create compatibility between the old RO/RW images from Volteer and the current coreboot ToT. That really only makes sense if you can't change the RO anymore (because it's write-protected)... but you're making a few changes to the RO here anyway, so clearly you'll still have to remove your write-protection and update your RO. So then why don't you just build both your alternative OS firmware and the ChromeOS firmware from ToT and then you don't have to worry about being compatible with some ancient image? Volteer should still build and boot fine in ToT for both coreboot and depthcharge (at least we're trying to keep it that way for all but the super old Chromebooks, and if something broke by accident it's usually an easy fix), so you can still build firmware that can "boot ChromeOS" but with the ToT coreboot code and RO/RW interface. And for that matter, I also don't think that the vboot RO/RW interface is the right point to select which OS you're booting. That's not really what it's designed for. It's designed to be the cut-off point between updateable and non-updateable firmware, but the differences between the two RW images (and the recovery RO image) are only supposed to be differences in which version of the code they're running, not what boot policy that code follows. If you want to change boot policy (and maybe make it controllable by a CMOS flag), that would probably belong in the payload according to the usual coreboot philosophy. In fact, we already have such a mechanism in our depthcharge payload that you could simply use for your purposes if you want to. It does pretty much what you want: it can boot either stock ChromeOS or a custom payload that you install, and which one it picks in the next boot can be controlled by a CMOS setting (except that this setting is in the vboot nvdata part of CMOS and you control it with our `crossystem` utility, by running `crossystem dev_default_boot=altfw` or `crossystem dev_default_boot=disk`). It will also display a UI on boot where you can select the boot target manually, but if you set the right GBB flag it will only show for 3 seconds before going with the default. See https://www.chromium.org/chromium-os/developer-library/guides/device/develo… for details on how to use that if you're interested. -- To view, visit https://review.coreboot.org/c/coreboot/+/81508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b26c332f5bf6befd62b5930b19d1b20e76261e7 Gerrit-Change-Number: 81508 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 00:53:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Support loading legacy stage
by Julius Werner (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Nick Vaccaro, Vladimir Serbinenko, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81505?usp=email ) Change subject: Support loading legacy stage ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Sorry, but I don't think it's worth adding this extra complexity to coreboot, because your underlying goal isn't really achievable in practice. The RO/RW interface is fundamentally not stable, and broken by dozens of changes every year — in ways that are often non-obvious and entirely platform-specific. For example any change to the CAR memory layout that shifts the position of some persistent buffers (like CB:79288), or any change to the format of any of these persistent buffers (vboot, TPM logs, CBFS and FMAP cache, etc.) will break it. You may have experimentally determined all the incompatibilities that currently exist to the Volteer RO for the moment, but more are going to be added in the future again, and what you did for Volteer will not automatically work for other boards that released at a different point in the past either. If we were really going to try to add compatibility options for all (or at least many) old ChromeOS boards we'd just be playing whack-a-mole forever and adding mountains of extra backwards-compatibility cruft to all parts of coreboot, and it still wouldn't work reliably anyway (and constantly break with hard crashes or worse whenever we miss an issue). The only way vboot's RO/RW mechanism is intended to work is that you cut a branch when you release the RO, and then you only ever release RW updates from that branch, and you only carefully cherry-pick individual patches where you've confirmed that they don't interfere with the RO/RW boundary to that branch. That's how we use it in ChromeOS, and our branches are public so if anyone wants to build new custom coreboot RW images that work with our existing released RO images, they are welcome to do that by basing them off that branch. If there's sufficient interest we could even try to maintain matching branches for each device upstream, or try to cut regular coreboot "LTS" branches that we then try to target with our Chromebook releases or something like that. But trying to make ToT compatible with every old release at once is futile, I think. -- To view, visit https://review.coreboot.org/c/coreboot/+/81505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae29a6227235c86f9f846986c18b361c3b3c78d Gerrit-Change-Number: 81505 Gerrit-PatchSet: 2 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 00:28:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by SH Kim (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 5: (2 comments) Patchset: PS5: One File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c: https://review.coreboot.org/c/coreboot/+/81436/comment/e9f3293b_237769f5 : PS5, Line 68: soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, How about writing 'soc_config->tdp_pl1_override' and 'soc_config->tdp_pl2_override' with the values in limits[i] here as well? After booting to ChromeOS, dptf_power_limits setting values will be replaced with DTT setting in OS. -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 26 Mar 2024 00:11:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cbfstool: Add printing of legacy stage type
by Julius Werner (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Vladimir Serbinenko. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81504?usp=email ) Change subject: cbfstool: Add printing of legacy stage type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I588028d4327f59538f7c9920b671458fc631cb4c Gerrit-Change-Number: 81504 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 23:54:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: superio/ite: Add special fan vectors and further options
by Joel Linn (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Matt DeVillier, Nico Huber. Joel Linn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81426?usp=email ) Change subject: superio/ite: Add special fan vectors and further options ...................................................................... Patch Set 5: (1 comment) File src/superio/ite/common/env_ctrl.c: https://review.coreboot.org/c/coreboot/+/81426/comment/2dd57016_10e3a6ba : PS1, Line 369: #endif > I still think keeping ITE_EC_FAN_VECTOR_CNT fixed at 2 and letting the preprocessor exclude the loop […] I implemented Matt's suggestion. Setting the array length to 0 would save only 12 bytes in the config struct. Granted we would still carry the dead code but that should also be in the order of tens of bytes. -- To view, visit https://review.coreboot.org/c/coreboot/+/81426?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94 Gerrit-Change-Number: 81426 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 23:35:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: superio/ite: Unify it8772f with common code
by Joel Linn (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Matt DeVillier, Michał Żygowski, MrChromebox, Nico Huber, Piotr Król. Joel Linn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81310?usp=email ) Change subject: superio/ite: Unify it8772f with common code ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > this is still a bit too much for a single patch, IMO the changes to the common code and non-8772F SI […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6 Gerrit-Change-Number: 81310 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: MrChromebox <mrchromebox(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 23:24:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: superio/ite: Fix warnings, add full-speed config option
by Joel Linn (Code Review) 25 Mar '24

25 Mar '24

Joel Linn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81516?usp=email ) Change subject: superio/ite: Fix warnings, add full-speed config option ...................................................................... superio/ite: Fix warnings, add full-speed config option Fix warning for disabled thermal inputs. Fix warning for PECI thermal inputs if one was set up previously. Depending on the mb, the superio will not go through power-on reset and retain its registers. Do not trigger a warning if the current register value aligns with the desired value. Don't return early if some input is already configured for PECI, simply overwrite the configuration. Add Kconfig option for full-speed setting. Some variants do not support the full-speed at limit configuration (IT8772F). Enable this for all current variants that use the common EC code as it was previously enabled unconditionally - datasheets weren't revisited individually. Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155 Signed-off-by: Joel Linn <jl(a)conductive.de> --- M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/it8613e/Kconfig M src/superio/ite/it8623e/Kconfig M src/superio/ite/it8629e/Kconfig M src/superio/ite/it8718f/Kconfig M src/superio/ite/it8720f/Kconfig M src/superio/ite/it8721f/Kconfig M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8772f/Kconfig M src/superio/ite/it8783ef/Kconfig M src/superio/ite/it8784e/Kconfig M src/superio/ite/it8786e/Kconfig 13 files changed, 31 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81516/1 diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 36c1496..21d3f18b 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -48,4 +48,9 @@ Temperature can be read to any TMPIN from an external sensor via SST/PECI (instead of TMPIN3 only). +config SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING + bool + help + Fans can be configured to run at full speed when limit temperature is reached + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 9149c58..b1a2362 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -67,6 +67,8 @@ reg_extra = pnp_read_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE); switch (conf->mode) { + case THERMAL_MODE_DISABLED: + return; case THERMAL_PECI: /* Some chips can set any TMPIN as the target for PECI readings while others can only read to TMPIN3. In the latter case a @@ -78,12 +80,15 @@ "PECI to TMPIN2 not supported on IT8721F\n"); return; } - if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) { + u8 reg_new = (reg & ~ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK) + | ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin); + /* Registers stick on reboot and resume, + don't warn for correct reg values */ + if (reg & ITE_EC_ADC_TEMP_EXT_REPORTS_TO_MASK && reg != reg_new) { printk(BIOS_WARNING, - "PECI specified for multiple TMPIN\n"); - return; + "PECI specified for another TMPIN, overwriting\n"); } - reg |= ITE_EC_ADC_TEMP_EXT_REPORTS_TO(tmpin); + reg = reg_new; } else if (tmpin == 3) { reg_extra |= ITE_EC_ADC_TEMP_EXTRA_TMPIN3_EXT; pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE, @@ -177,7 +182,8 @@ conf->tmp_full ? conf->tmp_full : 127); delta_temp = ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta); - delta_temp |= ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(conf->full_lmt); + if (CONFIG(SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING)) + delta_temp |= ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(conf->full_lmt); pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), delta_temp); } diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index e6f01c4..625e603 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -9,3 +9,4 @@ select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_NO_ONOFF select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING diff --git a/src/superio/ite/it8623e/Kconfig b/src/superio/ite/it8623e/Kconfig index 44a79ec..0a576ef 100644 --- a/src/superio/ite/it8623e/Kconfig +++ b/src/superio/ite/it8623e/Kconfig @@ -6,5 +6,6 @@ select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8629e/Kconfig b/src/superio/ite/it8629e/Kconfig index 29e72b6..0fe183e 100644 --- a/src/superio/ite/it8629e/Kconfig +++ b/src/superio/ite/it8629e/Kconfig @@ -6,6 +6,7 @@ select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_5FANS # TODO: Add support for 6 fans select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG diff --git a/src/superio/ite/it8718f/Kconfig b/src/superio/ite/it8718f/Kconfig index 65fcdab..1e40075 100644 --- a/src/superio/ite/it8718f/Kconfig +++ b/src/superio/ite/it8718f/Kconfig @@ -5,4 +5,5 @@ select SUPERIO_ITE_COMMON_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 diff --git a/src/superio/ite/it8720f/Kconfig b/src/superio/ite/it8720f/Kconfig index 338ed21..54ff317 100644 --- a/src/superio/ite/it8720f/Kconfig +++ b/src/superio/ite/it8720f/Kconfig @@ -5,4 +5,5 @@ select SUPERIO_ITE_COMMON_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 diff --git a/src/superio/ite/it8721f/Kconfig b/src/superio/ite/it8721f/Kconfig index ec22a2d..c6c0cb8 100644 --- a/src/superio/ite/it8721f/Kconfig +++ b/src/superio/ite/it8721f/Kconfig @@ -7,3 +7,4 @@ select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index 6d02c0b..8987f64 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -10,3 +10,4 @@ select SUPERIO_ITE_ENV_CTRL_5FANS select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index 194c736..3b4180e 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -3,3 +3,8 @@ config SUPERIO_ITE_IT8772F bool select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 diff --git a/src/superio/ite/it8783ef/Kconfig b/src/superio/ite/it8783ef/Kconfig index e1d993f..0c0ba51 100644 --- a/src/superio/ite/it8783ef/Kconfig +++ b/src/superio/ite/it8783ef/Kconfig @@ -5,4 +5,5 @@ select SUPERIO_ITE_COMMON_PRE_RAM select SUPERIO_ITE_ENV_CTRL select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 diff --git a/src/superio/ite/it8784e/Kconfig b/src/superio/ite/it8784e/Kconfig index 66dd6c9..75ef767 100644 --- a/src/superio/ite/it8784e/Kconfig +++ b/src/superio/ite/it8784e/Kconfig @@ -8,3 +8,4 @@ select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig index 216d6f5..3ca6fe8 100644 --- a/src/superio/ite/it8786e/Kconfig +++ b/src/superio/ite/it8786e/Kconfig @@ -8,3 +8,4 @@ select SUPERIO_ITE_ENV_CTRL_8BIT_PWM select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN + select SUPERIO_ITE_ENV_CTRL_FULLSPEED_SETTING -- To view, visit https://review.coreboot.org/c/coreboot/+/81516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155 Gerrit-Change-Number: 81516 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024