coreboot-gerrit March 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add SOC_INTEL_HAS_NUMA
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Chen, Gang C, Ziang Wang. Hello Chen, Gang C, Ziang Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81439?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Add SOC_INTEL_HAS_NUMA ...................................................................... soc/intel/xeon_sp: Add SOC_INTEL_HAS_NUMA NUMA and CXL supports are two different but correlated concepts. Add new Kconfig option to handle them separately. When SOC_INTEL_HAS_CXL selected, SOC_INTEL_HAS_NUMA will be selected. Change-Id: I84f07c16e24e441a885144df8c805f1310acae29 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/gnr/Kconfig M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c 10 files changed, 39 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81439/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 281d45a..17fd956 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -113,7 +113,11 @@ config HAVE_IOAT_DOMAINS bool +config SOC_INTEL_HAS_NUMA + bool + config SOC_INTEL_HAS_CXL + select SOC_INTEL_HAS_NUMA bool endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index eb39182..e0f96cd 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -14,7 +14,8 @@ ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c -ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c +ramstage-$(CONFIG_SOC_INTEL_HAS_NUMA) += numa.c +ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += smihandler.c pmutil.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 51e545f..c638801 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -9,6 +9,7 @@ select HAVE_INTEL_FSP_REPO select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select UDK_202005_BINDING + select SOC_INTEL_HAS_NUMA help Intel Cooper Lake-SP support diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 2d6005b..3472d58 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -136,3 +136,8 @@ { return true; } + +uint8_t get_cxl_node_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig index 1945be7..481a47a 100644 --- a/src/soc/intel/xeon_sp/gnr/Kconfig +++ b/src/soc/intel/xeon_sp/gnr/Kconfig @@ -17,6 +17,7 @@ select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select VPD select OCP_VPD + select SOC_INTEL_HAS_CXL help Intel GraniteRapids support diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 62657dc..0186865 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -50,7 +50,6 @@ /* Fill in processor domains */ uint8_t i, j, socket; - struct device *dev; for (socket = 0, i = 0; i < num_sockets; socket++) { if (!soc_cpu_is_enabled(socket)) continue; @@ -73,6 +72,7 @@ if (num_cxlnodes == 0) return; +#if CONFIG(SOC_INTEL_HAS_CXL) /* There are CXL nodes, fill in generic initiator domain after the processors pds */ uint8_t skt_id, cxl_id; const CXL_NODE_SOCKET *cxl_hob = get_cxl_node(); @@ -83,7 +83,7 @@ pds.pds[i].socket_bitmap = node.SocketBitmap; pds.pds[i].base = node.Address; pds.pds[i].size = node.Size; - dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0); + struct device *dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0); pds.pds[i].dev = dev; pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) @@ -97,6 +97,7 @@ } } } +#endif } /* diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 4a9e683..462e59f 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,6 +6,7 @@ select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT select UDK_202005_BINDING + select SOC_INTEL_HAS_NUMA help Intel Skylake-SP support diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 38d834f..5167a70 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -210,3 +210,8 @@ { return true; } + +uint8_t get_cxl_node_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 1d6d955..9a60805 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -281,7 +281,7 @@ { int index = 0; - if (CONFIG(SOC_INTEL_HAS_CXL)) { + if (CONFIG(SOC_INTEL_HAS_NUMA)) { static bool once; if (!once) { /* Construct NUMA data structure. This is needed for CXL. */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index c88707e..17c25a5 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -574,21 +574,23 @@ const config_t *const config = config_of(device); - /* SRAT */ - current = ALIGN_UP(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *)current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); + if (CONFIG(SOC_INTEL_HAS_NUMA)) { + /* SRAT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *)current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); - /* SLIT */ - current = ALIGN_UP(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *)current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); + /* SLIT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *)current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } if (CONFIG(SOC_INTEL_HAS_CXL)) { /* HMAT*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/81439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84f07c16e24e441a885144df8c805f1310acae29 Gerrit-Change-Number: 81439 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Subrata Banik (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim, Sumeet R Pawnikar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c: https://review.coreboot.org/c/coreboot/+/81436/comment/0fc0c84f_e73cc8b5 : PS5, Line 68: soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, > The override table has PL1/PL2 min/max values. I thought user might wish to override PL1/PL2 not only for MMIO register but MSR too, but I'm not sure about the original purpose of this code. > Someone to confirm it to add override tdp_pl1_override and tdp_pl2_override here? added Sumeet from Intel thermal side to commit (if any). -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 26 Mar 2024 06:56:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Subrata Banik (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81437/comment/9d237f43_897567a8 : PS2, Line 9: For dram_type 21 the switch case in use_ddr4_params : function falls to default. This adds SPD_DRAM_LPDDR5X dram_type : case to switch case block for dram_type 21 in the function. > Please use 72 characters per line (besides pasted lines). > > Please state the user visible problem: > > On google/brox, coreboot currently logs the line below. > > [NOTE ] Defaulting to using DDR4 params. Please add dram_type check for 21 to use_ddr4_params > > Follow the instruction, and add the macro SPD_DRAM_LPDDR5X in `use_ddr4_params()`. exactly. this is how you should write the commit msg to highlight a user visible problem and what fix u r providing. -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 06:55:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa: Create sundance variant
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81347?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa: Create sundance variant ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81347/comment/ce337472_d17fbf82 : PS7, Line 2: leo.chou Please use Leo Chou. $ git config --global user.name "Leo Chou" $ git commit --amend --author="Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>" -s https://review.coreboot.org/c/coreboot/+/81347/comment/420416df_039e1c55 : PS7, Line 12: in : inside What do you mean? -- To view, visit https://review.coreboot.org/c/coreboot/+/81347?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Gerrit-Change-Number: 81347 Gerrit-PatchSet: 7 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 06:54:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa: Create sundance variant
by Derek Huang (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81347?usp=email ) Change subject: mb/google/nissa: Create sundance variant ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81347?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Gerrit-Change-Number: 81347 Gerrit-PatchSet: 7 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 06:50:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81437/comment/73d18676_3587cc4f : PS2, Line 9: For dram_type 21 the switch case in use_ddr4_params : function falls to default. This adds SPD_DRAM_LPDDR5X dram_type : case to switch case block for dram_type 21 in the function. Please use 72 characters per line (besides pasted lines). Please state the user visible problem: On google/brox, coreboot currently logs the line below. [NOTE ] Defaulting to using DDR4 params. Please add dram_type check for 21 to use_ddr4_params Follow the instruction, and add the macro SPD_DRAM_LPDDR5X in `use_ddr4_params()`. -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 06:04:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Eric Lai (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Dinesh Gehlot, Garen Wu, Henry Sun, Kapil Porwal, Nick Vaccaro, Rasheed Hsueh. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) Change subject: mb/google/brya: Create yavista variant ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 9 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 05:56:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Garen Wu, Henry Sun, Kapil Porwal, Nick Vaccaro, Rasheed Hsueh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) Change subject: mb/google/brya: Create yavista variant ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 9 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 05:54:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/corsola: Add new board 'Kyogre'
by Paul Menzel (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Hung-Te Lin, Kei Hiroyoshi, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81218?usp=email ) Change subject: mb/google/corsola: Add new board 'Kyogre' ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81218/comment/bfd0498e_4f293a24 : PS4, Line 7: board board variant https://review.coreboot.org/c/coreboot/+/81218/comment/2fa3ee5f_c95f9dde : PS4, Line 9: follower What does “follower” mean? https://review.coreboot.org/c/coreboot/+/81218/comment/0d36d428_b81cec7b : PS4, Line 14: Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Please add a Signed-off-by line. Patchset: PS4: Welcome to coreboot! Thank you for your contribution. Feel free to contact the mailing list or the IRC channel [1] in case you have questions. If you addressed a comment, please “resolve” them by ticking the checkbox *Resolved*. [1]: https://doc.coreboot.org/community/forums.html -- To view, visit https://review.coreboot.org/c/coreboot/+/81218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Gerrit-Change-Number: 81218 Gerrit-PatchSet: 4 Gerrit-Owner: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kenny Pan <kennypan(a)google.com> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 05:50:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by SH Kim (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c: https://review.coreboot.org/c/coreboot/+/81436/comment/b084022b_f4bb1100 : PS5, Line 68: soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, > > How about writing 'soc_config->tdp_pl1_override' and 'soc_config->tdp_pl2_override' with the value […] The override table has PL1/PL2 min/max values. I thought user might wish to override PL1/PL2 not only for MMIO register but MSR too, but I'm not sure about the original purpose of this code. Someone to confirm it to add override tdp_pl1_override and tdp_pl2_override here? -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 26 Mar 2024 04:38:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: comment

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