coreboot-gerrit March 2024

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[M] Change in coreboot[main]: Support for creating hybrid vboot images
by Vladimir Serbinenko (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Julius Werner, Nick Vaccaro, Vladimir Serbinenko, Yu-Ping Wu. Hello Julius Werner, Nick Vaccaro, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81508?usp=email to look at the new patch set (#4). Change subject: Support for creating hybrid vboot images ...................................................................... Support for creating hybrid vboot images This allows creating an image where RO is triggered by default with normal RW secrets locked out. On a signal in CMOS, clear the signal and follow normal RW_A/RW_B path. This allows dual-boot between stock ChromeOS and an alternative payload while keeping compatibility with ChromeOS updates. Change-Id: I9b26c332f5bf6befd62b5930b19d1b20e76261e7 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/mainboard/google/volteer/Kconfig M src/security/vboot/Kconfig M src/security/vboot/misc.h M src/security/vboot/vboot_common.h M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c M src/soc/intel/common/block/cse/cse_eop.c 8 files changed, 121 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/81508/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b26c332f5bf6befd62b5930b19d1b20e76261e7 Gerrit-Change-Number: 81508 Gerrit-PatchSet: 4 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: cpu/x86/topology: Add node ID parser
by Arthur Heymans (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81515?usp=email ) Change subject: cpu/x86/topology: Add node ID parser ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Gerrit-Change-Number: 81515 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 19:32:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/x86/topology: Add node ID parser
by Patrick Rudolph (Code Review) 25 Mar '24

25 Mar '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81515?usp=email ) Change subject: cpu/x86/topology: Add node ID parser ...................................................................... cpu/x86/topology: Add node ID parser Currently the SRAT table only exposes one proximity group as it uses the LAPIC node_id, which is always initialized to 0. Use CPUID leaf 0x1f or 0xb to gather the node ID and fill it to make sure that at least one proximity group for every socket is advertised. For now the SNC config isn't taken into account. Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/topology.c M src/include/cpu/x86/topology.h M src/soc/intel/xeon_sp/spr/cpu.c 3 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/81515/1 diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c index 6c8d7fd..baa4a7a 100644 --- a/src/cpu/x86/topology.c +++ b/src/cpu/x86/topology.c @@ -4,6 +4,8 @@ #include <device/device.h> #include <cpu/x86/topology.h> +#define CPUID_EXTENDED_CPU_TOPOLOGY2 0x1f + #define CPUID_EXTENDED_CPU_TOPOLOGY 0x0b #define LEVEL_TYPE_CORE 2 #define LEVEL_TYPE_SMT 1 @@ -21,6 +23,64 @@ #define CPUID_CPU_TOPOLOGY_CORE_BITS(res, threadbits) \ ((CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax)) - threadbits) +/* Return the level shift for the highest supported level (the package) */ +static enum cb_err get_cpu_package_bits(uint32_t *package_bits) +{ + struct cpuid_result cpuid_regs; + int level_num, cpu_id_op = 0; + const uint32_t cpuid_max_func = cpuid_get_max_func(); + + /* + * Not all CPUs support this, those won't get topology filled in here. + * CPU specific code can do this however. + */ + if (cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY2) + cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY2; + else if (cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY) + cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY; + else + return CB_ERR; + + *package_bits = level_num = 0; + cpuid_regs = cpuid_ext(cpu_id_op, level_num); + + /* + * Sub-leaf index 0 enumerates SMT level, some AMD CPUs leave this CPUID leaf + * reserved so bail out. Cpu specific code can fill in the topology later. + */ + if (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) != LEVEL_TYPE_SMT) + return CB_ERR; + + do { + *package_bits = (CPUID_CPU_TOPOLOGY(LEVEL_BITS, (cpuid_regs).eax)); + level_num++; + cpuid_regs = cpuid_ext(cpu_id_op, level_num); + /* Stop when level type is invalid i.e 0. */ + } while (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs)); + + return CB_SUCCESS; +} + +void set_cpu_node_id_leaf_1f_b(struct device *cpu) +{ + static uint32_t package_bits; + static enum cb_err package_bits_ret; + static bool done = false; + + if (!done) { + package_bits_ret = get_cpu_package_bits(&package_bits); + done = true; + } + + const uint32_t apicid = cpu->path.apic.initial_lapicid; + + /* + * If leaf_1f or leaf_b does not exist don't update the node_id. + */ + if (package_bits_ret == CB_SUCCESS) + cpu->path.apic.node_id = (apicid >> package_bits); +} + /* Get number of bits for core ID and SMT ID */ static enum cb_err get_cpu_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) { diff --git a/src/include/cpu/x86/topology.h b/src/include/cpu/x86/topology.h index db29d09..d66f2eb 100644 --- a/src/include/cpu/x86/topology.h +++ b/src/include/cpu/x86/topology.h @@ -11,4 +11,9 @@ */ void set_cpu_topology_from_leaf_b(struct device *cpu); +/* Fill in the topology node ID in struct path APIC based CPUID EAX=0x1f + * or CPUID EAX=0xb. If those leaves aren't supported then the node ID + * won't be updated. + */ +void set_cpu_node_id_leaf_1f_b(struct device *cpu); #endif diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index 2ed8e22..f9c8e26 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -14,6 +14,7 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/topology.h> #include <device/pci_mmio_cfg.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> @@ -82,6 +83,10 @@ __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, cpu->path.apic.package_id); + /* Populate the node ID. It will be used as proximity ID. */ + set_cpu_node_id_leaf_1f_b(cpu); + assert (cpu->path.apic.node_id < CONFIG_MAX_SOCKET); + /* * Enable PWR_PERF_PLTFRM_OVR and PROCHOT_LOCK. * The value set by FSP is 20_005f, we set it to 1a_00a4_005b. -- To view, visit https://review.coreboot.org/c/coreboot/+/81515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Gerrit-Change-Number: 81515 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Subrata Banik (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81437/comment/8a1c2857_494d33be : PS2, Line 13: Bug nit: BUG https://review.coreboot.org/c/coreboot/+/81437/comment/c67e0e1d_cc2b34be : PS2, Line 16: please capture the change in the AP log w/o and w/ your patch to state the difference what your patch is making. -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 17:46:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Shelley Chen (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian, Subrata Banik. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 17:35:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Felix Singer, Michał Żygowski, Nicholas Chin, Paul Menzel. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80853?usp=email to look at the new patch set (#3). Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E RS232) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports (somewhat) - PCI-E Resizable BAR (ReBAR) - VT-x (PCI-E passtrough, broken on stock) WIP/Broken: - PCI-E ASPM (even though I force-disabled it, I'm still getting AERs) - M.2 NGFF WiFi (should be working, but I lost my WiFi card while moving) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (simple fix, need to re-configure GPIOs) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor haven't enabled any protections on SPI chip. I'd like to get ASPM working as it makes big difference in idle power consumtion (25 vs 60W measured from the wall at 230V). Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot the machine without `pcie_aspm=off` parameter: - BadTLP - BadDLLP - Timeout - Rollover Adjusting LaneEq's didn't change anything, all settings are configured in (mostly) the same way as they were on stock firmware. Starting to suspect Intel's FSP might be buggy, as I haven't had those issues when I initially started working on this project when 4.20 tree was current. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.7.4) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.inc A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 856 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 3 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Ashish Kumar Mishra (Code Review) 25 Mar '24

25 Mar '24

Ashish Kumar Mishra has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params For dram_type 21 the switch case in use_ddr4_params function falls to default. This adds SPD_DRAM_LPDDR5X dram_type case to switch case block for dram_type 21 in the function. Bug=None BRANCH=None TEST=Boot brox SKU1/SKU2 and verify logs for default case Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/lib/spd_bin.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/81437/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Ashish Kumar Mishra (Code Review) 25 Mar '24

25 Mar '24

Ashish Kumar Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params For dram_type 21 the switch case in use_ddr4_params function falls to default. This adds SPD_DRAM_LPDDR5X dram_type case to switch case block for dram_type 21 in the function. Bug=None BRANCH=None TEST=Boot SKU1/SKU2 and verify logs for default case Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/lib/spd_bin.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/81437/1 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index e005ccb..01f451d 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -35,6 +35,7 @@ case SPD_DRAM_DDR4: case SPD_DRAM_DDR5: case SPD_DRAM_LPDDR5: + case SPD_DRAM_LPDDR5X: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: return true; -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 1 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd/non_car/memlayout_x86.ld: Top align the code
by Arthur Heymans (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81433?usp=email ) Change subject: soc/amd/non_car/memlayout_x86.ld: Top align the code ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Tested with google/vilboz -- To view, visit https://review.coreboot.org/c/coreboot/+/81433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18bdf262f9c358aa01795b11efcb863686edc79c Gerrit-Change-Number: 81433 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 25 Mar 2024 17:12:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: arch/riscv: remove misaligned load/store/fetch handling
by Maximilian Brune (Code Review) 25 Mar '24

25 Mar '24

Attention is currently required from: Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81416?usp=email ) Change subject: arch/riscv: remove misaligned load/store/fetch handling ...................................................................... Patch Set 6: (1 comment) File src/arch/riscv/trap_handler.c: https://review.coreboot.org/c/coreboot/+/81416/comment/d7966e32_10f70a39 : PS4, Line 140: case CAUSE_ILLEGAL_INSTRUCTION: > Done Now you added it to the commit-msg, but you moved it back to its original state? -- To view, visit https://review.coreboot.org/c/coreboot/+/81416?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46 Gerrit-Change-Number: 81416 Gerrit-PatchSet: 6 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Mar 2024 17:04:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2024