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Hello Arthur Heymans, Philipp Hug, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
The following approvals got outdated and were removed:
Code-Review+1 by Philipp Hug, Verified+1 by build bot (Jenkins)
Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
mb/emulation/qemu-riscv: Change to -bios option
This changes the virt target so that it can be run with the -bios option
and a pflash backend for the flash. QEMU can now be run as follows:
qemu -M virt -m 1G -nographic -bios build/coreboot.rom \
-drive if=pflash,file=./build/coreboot.rom,format=raw
coreboot will start in DRAM, but still have a flash to put CBFS onto and
to load subsequent stages and payload from.
Tested bootflow:
coreboot -> OpenSBI -> Linux -> u-root
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d
---
M Documentation/mainboard/emulation/qemu-riscv.md
M src/mainboard/emulation/Kconfig
M src/mainboard/emulation/qemu-riscv/Kconfig
M src/mainboard/emulation/qemu-riscv/Makefile.mk
A src/mainboard/emulation/qemu-riscv/cbmem.c
A src/mainboard/emulation/qemu-riscv/chip.c
M src/mainboard/emulation/qemu-riscv/devicetree.cb
M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
M src/mainboard/emulation/qemu-riscv/mainboard.c
M src/mainboard/emulation/qemu-riscv/memlayout.ld
M src/mainboard/emulation/qemu-riscv/rom_media.c
M src/mainboard/emulation/qemu-riscv/romstage.c
M util/qemu/Makefile.mk
13 files changed, 98 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80746/7
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Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80703?usp=email )
Change subject: cpu/x86/smm: Pass full SMRAM region info to SMM runtime
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/google/guybrush: turn off SD ASPM L1.1/L1.2
......................................................................
Patch Set 7: Code-Review+2
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Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/emulation/qemu-riscv/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/80746/comment/872207f3_b31d513c :
PS6, Line 9: REGION(flash, QEMU_VIRT_FLASH, 32M, 0) \
use CONFIG_ROM_SIZE here?
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Change subject: mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/guybrush: turn off SD ASPM L1.1/L1.2
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80237/comment/c9f2bcf4_a501cf3b :
PS6, Line 11: BUG=b:254382832
: TEST=test pass over 10k cycles
> These lines need to go after the power numbers and before the `Signed-off-by`.
Done
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Hello Felix Held, Jason Nien, Martin Roth, Matt DeVillier, Matt DeVillier, Tim Van Patten, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80237?usp=email
to look at the new patch set (#7).
Change subject: mb/google/guybrush: turn off SD ASPM L1.1/L1.2
......................................................................
mb/google/guybrush: turn off SD ASPM L1.1/L1.2
Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure
We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests:
L1ss disabled SD plugged power idle test: 735.3875
L1ss enabled SD plugged power idle test: 737.2335
L1ss disabled SD plugged power video test: 333.29325
L1ss enabled SD plugged power video test: 333.442
BUG=b:254382832
TEST=test pass over 10k cycles
Signed-off-by: Jason Nien <finaljason(a)gmail.com>
Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9
---
M src/mainboard/google/guybrush/port_descriptors.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/80237/7
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Change subject: mb/google/guybrush: turn off SD ASPM L1.1/L1.2
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80237/comment/9374e3cd_0219ff4b :
PS6, Line 11: BUG=b:254382832
: TEST=test pass over 10k cycles
These lines need to go after the power numbers and before the `Signed-off-by`.
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