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Hello Arthur Heymans, Philipp Hug, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80746?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Code-Review+2 by ron minnich, Verified+1 by build bot (Jenkins)
Change subject: mb/emulation/qemu-riscv: Change to -bios option
......................................................................
mb/emulation/qemu-riscv: Change to -bios option
This changes the virt target so that it can be run with the -bios option
and a pflash backend for the flash. QEMU can now be run as follows:
qemu -M virt -m 1G -nographic -bios build/coreboot.rom \
-drive if=pflash,file=./build/coreboot.rom,format=raw
coreboot will start in DRAM, but still have a flash to put CBFS onto and
to load subsequent stages and payload from.
Tested bootflow:
coreboot -> OpenSBI -> Linux -> u-root
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d
---
M Documentation/mainboard/emulation/qemu-riscv.md
M src/mainboard/emulation/Kconfig
M src/mainboard/emulation/qemu-riscv/Kconfig
M src/mainboard/emulation/qemu-riscv/Makefile.mk
A src/mainboard/emulation/qemu-riscv/cbmem.c
A src/mainboard/emulation/qemu-riscv/chip.c
M src/mainboard/emulation/qemu-riscv/devicetree.cb
M src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
M src/mainboard/emulation/qemu-riscv/mainboard.c
M src/mainboard/emulation/qemu-riscv/memlayout.ld
M src/mainboard/emulation/qemu-riscv/rom_media.c
M src/mainboard/emulation/qemu-riscv/romstage.c
M util/qemu/Makefile.mk
13 files changed, 88 insertions(+), 58 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80746/6
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Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d
Gerrit-Change-Number: 80746
Gerrit-PatchSet: 6
Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>
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Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81028?usp=email )
Change subject: soc/intel/alderlake: Hide PMC and IOM devices
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Why we are hiding them again? check this out https://review.coreboot.org/c/coreboot/+/74850
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80717?usp=email )
Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
nb/haswell: Disable iGPU when dGPU is used
This is usually is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is installed. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.
This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).
This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info(a)minifree.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/northbridge/intel/haswell/gma.c
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Nico Huber: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 6e6948b..48a0ba5 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -461,12 +461,19 @@
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
}
+static void gma_func0_disable(struct device *dev)
+{
+ /* Disable VGA decode */
+ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
+}
+
static struct device_operations gma_func0_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
.acpi_fill_ssdt = gma_generate_ssdt,
+ .vga_disable = gma_func0_disable,
.ops_pci = &pci_dev_ops_pci,
};
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Attention is currently required from: Bao Zheng, Marshall Dawson, Martin Roth, Zheng Bao.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78311?usp=email )
Change subject: amdfwtool: Move code related to getting options to a new file
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
Patchset:
PS8:
looks like this patch needs a manual rebase
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Change subject: mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> > this change will break Linux and windows functionality. […]
if the issue is the touchscreen being powered on before BL_EN, then I ask again:
- when is BL_EN enabled?
- what drives it?
- can we drive BL_EN high earlier instead?
- does this issue affect other boards?
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Change subject: soc/intel/alderlake: Hide PMC and IOM devices
......................................................................
Set Ready For Review
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80755?usp=email )
Change subject: mb/system76/adl: Remove duplicate PchHdaAudioLinkHdaEnable
......................................................................
mb/system76/adl: Remove duplicate PchHdaAudioLinkHdaEnable
This UPD is hooked up in devicetree since commit 854bd492fcfa
("mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree").
As these boards were in development when the change happened, they still
had the UPD set via romstage. Remove them now so they are only set in
devicetree.
Change-Id: I393e2c7b0134a31feae20f8992d7fd447ff7ee59
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80755
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jeremy Soller <jeremy(a)system76.com>
---
M src/mainboard/system76/adl/variants/lemp11/romstage.c
M src/mainboard/system76/adl/variants/oryp10/romstage.c
M src/mainboard/system76/adl/variants/oryp9/romstage.c
3 files changed, 0 insertions(+), 3 deletions(-)
Approvals:
Nico Huber: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Jeremy Soller: Looks good to me, approved
diff --git a/src/mainboard/system76/adl/variants/lemp11/romstage.c b/src/mainboard/system76/adl/variants/lemp11/romstage.c
index 989b5df..211ab97 100644
--- a/src/mainboard/system76/adl/variants/lemp11/romstage.c
+++ b/src/mainboard/system76/adl/variants/lemp11/romstage.c
@@ -15,7 +15,6 @@
};
const bool half_populated = false;
- mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
diff --git a/src/mainboard/system76/adl/variants/oryp10/romstage.c b/src/mainboard/system76/adl/variants/oryp10/romstage.c
index 48714e0..86ecf32 100644
--- a/src/mainboard/system76/adl/variants/oryp10/romstage.c
+++ b/src/mainboard/system76/adl/variants/oryp10/romstage.c
@@ -23,7 +23,6 @@
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
- mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
diff --git a/src/mainboard/system76/adl/variants/oryp9/romstage.c b/src/mainboard/system76/adl/variants/oryp9/romstage.c
index d16b4f8..5e6cf7d 100644
--- a/src/mainboard/system76/adl/variants/oryp9/romstage.c
+++ b/src/mainboard/system76/adl/variants/oryp9/romstage.c
@@ -20,7 +20,6 @@
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
- mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
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