coreboot-gerrit March 2024

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Philipp Hug (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, ron minnich. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 6: Code-Review+1 (4 comments) File src/mainboard/emulation/qemu-riscv/Makefile.mk: https://review.coreboot.org/c/coreboot/+/80746/comment/20f138ae_192cce05 : PS6, Line 7: bootblock-y += cbmem.c no need to move them to bootblock-y, those can stay romstage-y, to allow both with and without separate romstage File src/mainboard/emulation/qemu-riscv/memlayout.ld: https://review.coreboot.org/c/coreboot/+/80746/comment/72eef9a5_de0e0460 : PS6, Line 20: #if ENV_SEPARATE_ROMSTAGE romstage can be placed at same place as opensbi to keep separate romstage support File src/mainboard/emulation/qemu-riscv/romstage.c: https://review.coreboot.org/c/coreboot/+/80746/comment/1b130a27_319c897c : PS6, Line 9: console_init(); add main to allow both with and without separate romstage: #if CONFIG(SEPARATE_ROMSTAGE) void main(void) { console_init(); romstage_main(); } #endif File util/qemu/Makefile.mk: https://review.coreboot.org/c/coreboot/+/80746/comment/26f55ef6_b620546f : PS6, Line 32: QEMU-$(CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64) ?= qemu-system-riscv64 -M virt -drive \ maybe add -m 1G as well here, as the default memory size is really low on riscv -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 16:26:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm: Pass full SMRAM region info to SMM runtime
by Benjamin Doron (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Shuo Liu, Tim Chu, Vanessa Eusebio. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80703?usp=email ) Change subject: cpu/x86/smm: Pass full SMRAM region info to SMM runtime ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80703/comment/0e10e1f9_e571f28e : PS2, Line 7: cpu/x86/smm/smm_module_loader.c: Pass full SMRAM region info to SMM runtime > I would suggest something like: […] Okay, sounds good. https://review.coreboot.org/c/coreboot/+/80703/comment/91a3e0b2_0dcf0981 : PS2, Line 17: integrity of the S3 resume path. > Sorry, I mean the current smm_region_overlaps_handler() only provides SMRAM, but not staging cache a […] Ah, I see what you're talking about. The stage cache and chipset area are all subregions of SMRAM, which also contains one more area: the handler. You can see how this calculated in tseg_region.c of this folder. The objective of this patch is to cover every subregion of SMRAM, not just the handler region. -- To view, visit https://review.coreboot.org/c/coreboot/+/80703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f Gerrit-Change-Number: 80703 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 16:14:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm: Pass full SMRAM region info to SMM runtime
by Benjamin Doron (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Tim Chu, Vanessa Eusebio. Hello Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Vanessa Eusebio, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80703?usp=email to look at the new patch set (#3). Change subject: cpu/x86/smm: Pass full SMRAM region info to SMM runtime ...................................................................... cpu/x86/smm: Pass full SMRAM region info to SMM runtime This data is used by smm_region_overlaps_handler(). Callers use this helper to determine if it's safe to read/write to memory buffers taken from untrusted input. coreboot SMI handlers must not be confused into writing over any SMRAM subregion, not just the handlers. If stage cache writes were permitted, this could compromise the integrity of the S3 resume path. The consequences to overwriting the chipset-specific area are undefined. Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/80703/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f Gerrit-Change-Number: 80703 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/guybrush: turn off SD ASPM L1.1/L1.2
by Tim Van Patten (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Felix Held, Jason Nein, Jason Nien, Martin Roth, Matt DeVillier. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80237?usp=email ) Change subject: mb/google/guybrush: turn off SD ASPM L1.1/L1.2 ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80237/comment/25320189_1dcf1c84 : PS2, Line 8: Please add the power numbers from the bug here as well: https://b.corp.google.com/issues/254382832#comment126 https://review.coreboot.org/c/coreboot/+/80237/comment/43525242_c4548a9f : PS2, Line 9: t Nit: Capitalize the first word: "Turn". -- To view, visit https://review.coreboot.org/c/coreboot/+/80237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Gerrit-Change-Number: 80237 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Nein <finaljason(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jason Nein <finaljason(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 04 Mar 2024 16:02:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Kapil Porwal (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Gwendal Grignou, Paul Menzel, Paz Zcharya, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Mar 2024 16:02:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/vpd: Add vpd_get_feature_level() API
by Kapil Porwal (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Gwendal Grignou, Nick Vaccaro, Shelley Chen, Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80805?usp=email ) Change subject: drivers/vpd: Add vpd_get_feature_level() API ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8 Gerrit-Change-Number: 80805 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Mon, 04 Mar 2024 16:01:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: SiFive Unmatched: add support for spi1 x4 mode
by ron minnich (Code Review) 04 Mar '24

04 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81031?usp=email ) Change subject: SiFive Unmatched: add support for spi1 x4 mode ...................................................................... SiFive Unmatched: add support for spi1 x4 mode Tested on an unmatched, both SPI1 x1 and x4 work now. Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/mainboard/sifive/hifive-unleashed/media.c M src/mainboard/sifive/hifive-unmatched/cbfs_spi.c 2 files changed, 29 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/81031/1 diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index a225dda..6a3878b 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -47,12 +47,13 @@ const struct region_device *boot_device_ro(void) { - uint32_t m = read32((uint32_t *)FU540_MSEL); - if (MSEL_SPI0x1(m) || MSEL_SPI0x4(m)) + uint32_t m = read32((uint32_t *)FU540_MSEL) & 0xf; + if (MSEL_SPI0x1(m) || MSEL_SPI0x4(m) || MSEL_SPI1x4(m)) return &spi_mdev.rdev; if (MSEL_SPI2SD(m)) return &sd_mdev.rdev; - die("Wrong configuration of MSEL\n"); + printk(BIOS_EMERG, "MSEL: %#02x", m); + die("Unsupported configuration of MSEL\n"); return NULL; } diff --git a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c index 787d8e7..f47da22 100644 --- a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c +++ b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c @@ -116,15 +116,34 @@ if (spi_flash_init_done == true) return; - uint32_t m = read32((uint32_t *)FU740_MSEL); + uint32_t m = read32((uint32_t *)FU740_MSEL) & 0xf; + printk(BIOS_DEBUG, "%s MSEL %#x\n", __func__, m); + + // We have not yet found a way to reliably program the + // on-board SPI part (sifive neglected to put a diode on vcc ...) + // Once we work that out, we can test this code. + // It is left here as a hint of what needs to be done. // Pass the information of the flash read operation to the spi controller - //.pad_cnt = 6, - if (MSEL_SPI0x4(m) || MSEL_SPI1x4(m)) { + if (MSEL_SPI0x4(m)) { + die("SPI0x4 is not supported yet"); //config.ffmt_config.data_proto = FU740_SPI_PROTO_Q; //config.ffmt_config.cmd_code = 0x6B; // Quad output read //.cmd_code = 0xec, + //.pad_cnt = 6, } - if (MSEL_SPI1x1(m)) { + if (MSEL_SPI1x4(m)) { + printk(BIOS_DEBUG, "%s SPI1x4 1\n", __func__); + fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_Q; + fu740_spi_configs[1].ffmt_config.cmd_code = 0x6b; // quad + if (spi_flash_probe(1, 0, &spi_flash)) { + printk(BIOS_EMERG, "SPI1x4 failed to init SPI flash\n"); + return; + } + if (fu740_spi_setup(&spi_flash.spi) == -1) { + printk(BIOS_EMERG, "SPI1x4 failed to configure mmap for SPI flash\n"); + } + printk(BIOS_DEBUG, "%s SPI1x4 2\n", __func__); + } else if (MSEL_SPI1x1(m)) { printk(BIOS_DEBUG, "%s 1\n", __func__); fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_S; fu740_spi_configs[1].ffmt_config.cmd_code = 0x03; // Normal read @@ -133,17 +152,12 @@ printk(BIOS_EMERG, "failed to init SPI flash\n"); return; } - // initialize soc spi controller - //if (fu740_spi_setup(&spi1_flash.spi) == -1) { - // printk(BIOS_EMERG, "failed to configure mmap for SPI flash\n"); - //} - //hexdump((void*)0x10041000, 0x100); - //hexdump((void*)0x30000000, 0x100); printk(BIOS_DEBUG, "%s 2\n", __func__); } else if (MSEL_SPI2SD(m)) { spi_sdcard_init(&spi2_sdcard, 2, 0); } else { - die("Wrong configuration of MSEL\n"); + printk(BIOS_EMERG, "MSEL: %#02x: ", m); + die("unsupported configuration of MSEL\n"); } spi_flash_init_done = true; -- To view, visit https://review.coreboot.org/c/coreboot/+/81031?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Gerrit-Change-Number: 81031 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: SiFive Unmatched: add support for spi1 x4 mode
by ron minnich (Code Review) 04 Mar '24

04 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81030?usp=email ) Change subject: SiFive Unmatched: add support for spi1 x4 mode ...................................................................... SiFive Unmatched: add support for spi1 x4 mode Tested on an unmatched, both SPI1 x1 and x4 work now. Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/mainboard/sifive/hifive-unleashed/media.c M src/mainboard/sifive/hifive-unmatched/cbfs_spi.c 2 files changed, 29 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/81030/1 diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index a225dda..6a3878b 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -47,12 +47,13 @@ const struct region_device *boot_device_ro(void) { - uint32_t m = read32((uint32_t *)FU540_MSEL); - if (MSEL_SPI0x1(m) || MSEL_SPI0x4(m)) + uint32_t m = read32((uint32_t *)FU540_MSEL) & 0xf; + if (MSEL_SPI0x1(m) || MSEL_SPI0x4(m) || MSEL_SPI1x4(m)) return &spi_mdev.rdev; if (MSEL_SPI2SD(m)) return &sd_mdev.rdev; - die("Wrong configuration of MSEL\n"); + printk(BIOS_EMERG, "MSEL: %#02x", m); + die("Unsupported configuration of MSEL\n"); return NULL; } diff --git a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c index 787d8e7..f47da22 100644 --- a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c +++ b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c @@ -116,15 +116,34 @@ if (spi_flash_init_done == true) return; - uint32_t m = read32((uint32_t *)FU740_MSEL); + uint32_t m = read32((uint32_t *)FU740_MSEL) & 0xf; + printk(BIOS_DEBUG, "%s MSEL %#x\n", __func__, m); + + // We have not yet found a way to reliably program the + // on-board SPI part (sifive neglected to put a diode on vcc ...) + // Once we work that out, we can test this code. + // It is left here as a hint of what needs to be done. // Pass the information of the flash read operation to the spi controller - //.pad_cnt = 6, - if (MSEL_SPI0x4(m) || MSEL_SPI1x4(m)) { + if (MSEL_SPI0x4(m)) { + die("SPI0x4 is not supported yet"); //config.ffmt_config.data_proto = FU740_SPI_PROTO_Q; //config.ffmt_config.cmd_code = 0x6B; // Quad output read //.cmd_code = 0xec, + //.pad_cnt = 6, } - if (MSEL_SPI1x1(m)) { + if (MSEL_SPI1x4(m)) { + printk(BIOS_DEBUG, "%s SPI1x4 1\n", __func__); + fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_Q; + fu740_spi_configs[1].ffmt_config.cmd_code = 0x6b; // quad + if (spi_flash_probe(1, 0, &spi_flash)) { + printk(BIOS_EMERG, "SPI1x4 failed to init SPI flash\n"); + return; + } + if (fu740_spi_setup(&spi_flash.spi) == -1) { + printk(BIOS_EMERG, "SPI1x4 failed to configure mmap for SPI flash\n"); + } + printk(BIOS_DEBUG, "%s SPI1x4 2\n", __func__); + } else if (MSEL_SPI1x1(m)) { printk(BIOS_DEBUG, "%s 1\n", __func__); fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_S; fu740_spi_configs[1].ffmt_config.cmd_code = 0x03; // Normal read @@ -133,17 +152,12 @@ printk(BIOS_EMERG, "failed to init SPI flash\n"); return; } - // initialize soc spi controller - //if (fu740_spi_setup(&spi1_flash.spi) == -1) { - // printk(BIOS_EMERG, "failed to configure mmap for SPI flash\n"); - //} - //hexdump((void*)0x10041000, 0x100); - //hexdump((void*)0x30000000, 0x100); printk(BIOS_DEBUG, "%s 2\n", __func__); } else if (MSEL_SPI2SD(m)) { spi_sdcard_init(&spi2_sdcard, 2, 0); } else { - die("Wrong configuration of MSEL\n"); + printk(BIOS_EMERG, "MSEL: %#02x: ", m); + die("unsupported configuration of MSEL\n"); } spi_flash_init_done = true; -- To view, visit https://review.coreboot.org/c/coreboot/+/81030?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Gerrit-Change-Number: 81030 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Patrick Rudolph (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug, ron minnich. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80746/comment/f97bf03e_f7b974ee : PS6, Line 9: bios Since which version is -bios supported in qemu? Is this change backwards compatible? -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 15:47:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Maximilian Brune (Code Review) 04 Mar '24

04 Mar '24

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > as discussed, rebase this on top of 36486 to avoid fixed RAM size Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2024 15:43:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: comment

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