coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: drivers/vpd: Add vpd_get_feature_level() API
by Gwendal Grignou (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Nick Vaccaro, Shelley Chen, Subrata Banik. Gwendal Grignou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80805?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/vpd: Add vpd_get_feature_level() API ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/drivers/vpd/vpd_device_feature.c: … [View More]

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[S] Change in coreboot[main]: mb/google/brya/var/dochi: Add wifi sar table
by Bob Moragues (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: David Wu, Dinesh Gehlot, Kapil Porwal, Morris Hsu, Nick Vaccaro. Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80809?usp=email ) Change subject: mb/google/brya/var/dochi: Add wifi sar table ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80809?usp=email To unsubscribe, or for help writing mail … [View More]

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[S] Change in coreboot[main]: cpu/x86/smm: Pass full SMRAM region info to SMM runtime
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Jeff Daly, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Tim Chu, Vanessa Eusebio. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80703?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: cpu/x86/smm: Pass full SMRAM region info to SMM runtime ...............… [View More]....................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80703/comment/f0be0df6_ab4d3ac8 : PS3, Line 16: If stage cache writes were permitted, this could compromise the let us add this to be more specific: SMRAM region includes TSEG_STAGE_CACHE and chipset-specific area (IED). If stage cache .... -- To view, visit https://review.coreboot.org/c/coreboot/+/80703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f Gerrit-Change-Number: 80703 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 00:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment [View Less]

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[S] Change in coreboot[main]: mb/google/brya/var/omniknight: remove Implement touchscreen power seq...
by Jamie Chen (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Ivan Chen, Kapil Porwal, Martin L Roth, Nick Vaccaro, Paul Menzel, Subrata Banik. Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80769?usp=email ) Change subject: mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing ...................................................................... Patch Set 7: (5 comments) Commit Message: https://review.coreboot.org/c/… [View More]coreboot/+/80769/comment/579494d5_fdcdee1d : PS7, Line 7: remove Implement > Remove Done https://review.coreboot.org/c/coreboot/+/80769/comment/69c591c6_3a347525 : PS7, Line 11: no > does not Done https://review.coreboot.org/c/coreboot/+/80769/comment/40a830f1_b5184415 : PS7, Line 11: #comment36 > Comment in what thread? https://partnerissuetracker.corp.google.com/issues/326337003#comment36 https://review.coreboot.org/c/coreboot/+/80769/comment/de383781_330867b5 : PS7, Line 11: pre > per Done https://review.coreboot.org/c/coreboot/+/80769/comment/c8d9cd1c_6e7356e4 : PS7, Line 12: it may have ghost touch > Sorry, I do not understand. https://partnerissuetracker.corp.google.com/issues/326337003#comment36 -- To view, visit https://review.coreboot.org/c/coreboot/+/80769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Gerrit-Change-Number: 80769 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 00:29:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment [View Less]

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[S] Change in coreboot[main]: amdfwtool: Set the table size for L1 separately
by Felix Held (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Bao Zheng, Martin Roth, Nikolai Vyssotski, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78274?usp=email ) Change subject: amdfwtool: Set the table size for L1 separately ...................................................................... Patch Set 12: Code-Review+1 (4 comments) Patchset: PS12: would be good to add a comment to the code to clarify things a bit, but apart from that the code … [View More]looks correct to me File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/78274/comment/992be749_26967440 : PS11, Line 615: 1 > This patch is only for family which PSP header points to ISH header. […] i thought of having one patch that changes the alignments and one that addresses the psp l1 size calculation in the ish case, but since this patch is about making sure that the l1 table size is correctly reported, that is something to maybe look into in a separate patch https://review.coreboot.org/c/coreboot/+/78274/comment/1bf8b44a_7a91cbcf : PS11, Line 655: if (cookie == PSP_COOKIE && cb_config->need_ish) : table_size = TABLE_ALIGNMENT; : else > In integrate_psp_firmwares the new_ish_dir is called. […] good point. had a look at the documentation and it says that in the ISH case, the PSP L1 directory table can have at most 32 entries, so setting table_size to TABLE_ALIGNMENT is valid in all cases so the code will result in the correct behavior. would be good to a comment here to make it easier to understand why this is done and correct by the spec File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/78274/comment/b9180903_305ba8fa : PS12, Line 576: uint32_t align_end = cb_config->need_ish ? TABLE_ALIGNMENT : 1; shouldn't the table be always aligned to TABLE_ALIGNMENT? i'm fine with leaving this as it is right now and doing that change in a follow-up patch; possibly together with the other alignment changes i suggested looking into -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 00:26:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment [View Less]

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[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Philipp Hug (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Patrick Rudolph. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit … [View More]

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Change in coreboot[master]: WIP: riscv/mb/qemu: fix DRAM probing
by Philipp Hug (Code Review) 05 Mar '24

05 Mar '24

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36486 ) Change subject: WIP: riscv/mb/qemu: fix DRAM probing ...................................................................... WIP: riscv/mb/qemu: fix DRAM probing Current version of qemu raise an exception when accessing invalid memory. Modify the probing code to temporary redirect the exception handler like on ARM platform. TEST=qemu detects RAM size correctly Change-Id: … [View More]I25860f688c7546714f6fdbce8c8f96da6400813c Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/Makefile.inc M src/arch/riscv/include/arch/exception.h A src/arch/riscv/ramdetect.c M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S M src/lib/ramdetect.c 6 files changed, 57 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/36486/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0039fab..7465a8f 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -101,6 +101,7 @@ romstage-y += stages.c romstage-y += misc.c romstage-$(ARCH_RISCV_PMP) += pmp.c +romstage-y += ramdetect.c romstage-y += smp.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -142,6 +143,7 @@ ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c +ramstage-y += ramdetect.c ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h index 6fbbdf0..cdca582 100644 --- a/src/arch/riscv/include/arch/exception.h +++ b/src/arch/riscv/include/arch/exception.h @@ -53,7 +53,7 @@ } void redirect_trap(void); -void trap_handler(trapframe *tf); +void default_trap_handler(trapframe *tf); void handle_supervisor_call(trapframe *tf); void handle_misaligned(trapframe *tf); diff --git a/src/arch/riscv/ramdetect.c b/src/arch/riscv/ramdetect.c new file mode 100644 index 0000000..47153ab --- /dev/null +++ b/src/arch/riscv/ramdetect.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/exception.h> +#include <types.h> +#include <console/console.h> +#include <device/mmio.h> +#include <ramdetect.h> +#include <arch/smp/spinlock.h> + +static enum { + ABORT_CHECKER_NOT_TRIGGERED, + ABORT_CHECKER_TRIGGERED, +} abort_state = ABORT_CHECKER_NOT_TRIGGERED; + +extern void(*trap_handler)(trapframe *tf); + +#define insn_size 4 +static void ramcheck_trap_handler(trapframe *tf) +{ + printk(BIOS_DEBUG, "TRAP 0x%lx!!!\n", tf->epc); + abort_state = ABORT_CHECKER_TRIGGERED; + + /* + * skip read instruction. + * currenctly hardcoded to 32bit instruction size + */ + write_csr(mepc, read_csr(mepc) + insn_size); +} + +int probe_mb(const uintptr_t dram_start, const uintptr_t size) +{ + uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t); + void *ptr = (void *)addr; + + abort_state = ABORT_CHECKER_NOT_TRIGGERED; + trap_handler = ramcheck_trap_handler; + barrier(); + read32(ptr); + trap_handler = default_trap_handler; + barrier(); + return abort_state == ABORT_CHECKER_NOT_TRIGGERED; +} diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 6b39fab..1d51268 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -118,7 +118,10 @@ break; } } -void trap_handler(trapframe *tf) + +void(*trap_handler)(trapframe *tf) = default_trap_handler; + +void default_trap_handler(trapframe *tf) { write_csr(mscratch, tf); if (tf->cause & 0x8000000000000000ULL) { diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 67e917c..93f5afd 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -120,7 +120,8 @@ save_tf mv a0, sp - jal trap_handler + ld t0, trap_handler + jalr t0 restore_regs addi sp, sp, MENTRY_FRAME_SIZE diff --git a/src/lib/ramdetect.c b/src/lib/ramdetect.c index 2c83092..eaf6190 100644 --- a/src/lib/ramdetect.c +++ b/src/lib/ramdetect.c @@ -58,6 +58,8 @@ if (saved_result) return saved_result; + printk(BIOS_DEBUG, "RAMDETECT: Starting\n"); + /* Find the MSB + 1. */ size_t tmp = probe_size; do { -- To view, visit https://review.coreboot.org/c/coreboot/+/36486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Gerrit-Change-Number: 36486 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange [View Less]

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[XS] Change in coreboot[main]: mb/google/guybrush: turn off SD ASPM L1.1/L1.2
by Matt DeVillier (Code Review) 05 Mar '24

05 Mar '24

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80237?usp=email ) Change subject: mb/google/guybrush: turn off SD ASPM L1.1/L1.2 ...................................................................... mb/google/guybrush: turn off SD ASPM L1.1/L1.2 Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests: L1ss disabled SD plugged … [View More]power idle test: 735.3875 L1ss enabled SD plugged power idle test: 737.2335 L1ss disabled SD plugged power video test: 333.29325 L1ss enabled SD plugged power video test: 333.442 BUG=b:254382832 TEST=test pass over 10k cycles Signed-off-by: Jason Nien <finaljason(a)gmail.com> Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80237 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Van Patten: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index fc6ccb8..a056a19 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -33,8 +33,8 @@ .device_number = PCI_SLOT(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN), .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, + .link_aspm_L1_1 = false, + .link_aspm_L1_2 = false, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, .gpio_group_id = GPIO_69, -- To view, visit https://review.coreboot.org/c/coreboot/+/80237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Gerrit-Change-Number: 80237 Gerrit-PatchSet: 8 Gerrit-Owner: Jason Nein <finaljason(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged [View Less]

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[XS] Change in coreboot[main]: LinuxBoot/targets/u-root.mk: Correct config for UROOT_ARCH
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77605?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: LinuxBoot/targets/u-root.mk: Correct config for UROOT_ARCH ...................................................................... LinuxBoot/targets/u-root.mk: Correct config for UROOT_ARCH The using config string for amd64 as UROOT_ARCH contains typo … [View More]

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[S] Change in coreboot[main]: payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH
by Felix Singer (Code Review) 04 Mar '24

04 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80726?usp=email ) Change subject: payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH ...................................................................... payloads/depthcharge: Add DEPTHCHARGE_REPO and DEPTHCHARGE_BRANCH Move hard-coded repo and repo name to Kconfig as default value DEPTHCHARGE_REPO default to: https://chromium.googlesource.com/chromiumos/platform/depthcharge … [View More]DEPTHCHARGE_BRANCH default to: origin/main When DEPTHCHARGE_MASTER=y, DEPTHCHARGE_BRANCH can be used to point out a particular branch. This change enable to use mirrored internal depthcharge repo and branch for early SOC development (before upstreaming SOC and dephthcharge code). TEST=Build coreboot and check the repo remote link from: payloads/external/depthcharge/depthcharge Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Icca10aa770b7b7a6e010f58bcf1e4f0a3401681a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80726 Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Zhixing Ma <zhixing.ma(a)intel.com> --- M payloads/external/Makefile.mk M payloads/external/depthcharge/Kconfig M payloads/external/depthcharge/Makefile 3 files changed, 16 insertions(+), 2 deletions(-) Approvals: Wonkyu Kim: Looks good to me, but someone else must approve Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Zhixing Ma: Looks good to me, but someone else must approve Bora Guvendik: Looks good to me, approved diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index c87f140..f1dc5cc 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -146,6 +146,8 @@ $(MAKE) -C payloads/external/depthcharge \ BOARD=$(BOARD) \ MFLAGS= MAKEFLAGS= \ + DEPTHCHARGE_REPO=$(CONFIG_DEPTHCHARGE_REPO) \ + DEPTHCHARGE_BRANCH=$(CONFIG_DEPTHCHARGE_BRANCH) \ DEPTHCHARGE_MASTER=$(CONFIG_DEPTHCHARGE_MASTER) \ DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \ DEPTHCHARGE_REVISION=$(CONFIG_DEPTHCHARGE_REVISION) \ diff --git a/payloads/external/depthcharge/Kconfig b/payloads/external/depthcharge/Kconfig index c531aa0..86b20ab 100644 --- a/payloads/external/depthcharge/Kconfig +++ b/payloads/external/depthcharge/Kconfig @@ -26,6 +26,18 @@ endchoice +config DEPTHCHARGE_REPO + string "depthcharge repo site" + default "https://chromium.googlesource.com/chromiumos/platform/depthcharge" + help + repo site + +config DEPTHCHARGE_BRANCH + string "branch from the depthcharge repo" + default "origin/main" + help + repo branch name + config DEPTHCHARGE_REVISION_ID string "Insert a commit's SHA-1 or a branch name" depends on DEPTHCHARGE_REVISION diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index e3e2303..af303da 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -3,7 +3,7 @@ project_name=depthcharge project_dir=$(CURDIR)/depthcharge -project_git_repo=https://chromium.googlesource.com/chromiumos/platform/depthcharge +project_git_repo=$(DEPTHCHARGE_REPO) project_config_file=$(project_dir)/.config output_dir=$(project_dir)/build libpayload_dir=$(abspath $(CURDIR)/../../libpayload) @@ -13,7 +13,7 @@ VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot) EC_HEADERS ?= $(abspath $(CURDIR)/../../../3rdparty/chromeec/include) -TAG-$(DEPTHCHARGE_MASTER)=origin/main +TAG-$(DEPTHCHARGE_MASTER)=$(DEPTHCHARGE_BRANCH) TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID) TAG-$(DEPTHCHARGE_REVISION)=$(DEPTHCHARGE_REVISION_ID) -- To view, visit https://review.coreboot.org/c/coreboot/+/80726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icca10aa770b7b7a6e010f58bcf1e4f0a3401681a Gerrit-Change-Number: 80726 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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