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Change subject: vc/amd/opensil/genoa_poc/memmap: use GiB define
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Create CXL domains
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Change subject: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> this should be the base CL.
It looks it is on my end. This the base of this relation chain, isn't ?
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Hello Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Martin L Roth, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80275?usp=email
to look at the new patch set (#24).
The following approvals got outdated and were removed:
Code-Review+1 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
......................................................................
drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It support 64-bits FSP but 64-bits support will be provided by
subsequent patch.
Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase.
[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf
[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-…
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/upd_display.c
M util/cbfstool/eventlog.c
10 files changed, 124 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/24
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Change subject: drivers/intel/fsp2_0/ppi: Fix FSP PPI callback calling convention
......................................................................
Patch Set 14:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80574/comment/f63d4607_cb46f0c4 :
PS7, Line 9: Multi Processor PEIM-to-PEIM Interface deals with pointer to function
: living in FSP space
> > > this is not correct, with a unified stack between FSP and coreboot. […]
Discarding a function type by casting to (Void *) and then calling is wrong IMO. It makes the assumption that the current compiler / system calling convention complies with the one original function type.
The fact it works is because the calling convention is the same but technically we should not discard it. That's what this code is fixing. Let's say for instance you want to compile coreboot with a Microsoft compiler using the stdcall calling convention by default, that piece of code would break even on 32-bits. From C point of view the current code is not correct as it relies on knowledge compiler of specifics which turns out to be fine because most of them just use the same C calling convention.
Honestly, I don't think there is any value debating this more. If you want me to move that to the 64-bits support patch then fine, I'll just to that.
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Change subject: arch/riscv: Add SMP support for exception handler
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Patch Set 8: Code-Review+2
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