coreboot-gerrit March 2024

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics
by Felix Held (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Anand Vaikar, Fred Reitberger, Martin L Roth, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81036?usp=email ) Change subject: mb/amd/birman_plus: Update glinda DXIO descriptors per schematics ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: looks good to me, but haven't checked the schematic yet -- To view, visit https://review.coreboot.org/c/coreboot/+/81036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If22e57fc57b4824550f2dfa8b843a7809c85dbb6 Gerrit-Change-Number: 81036 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 06 Mar 2024 17:13:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: [WIP] mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips
by Felix Held (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Fred Reitberger, Jason Glenesk. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81101?usp=email ) Change subject: [WIP] mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips ...................................................................... [WIP] mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips Add the stub MPIO chips that contain the PCIe engine configuration for the external PCIe interfaces to the devicetree. Birman's port_descriptors_phoenix.c was used as a reference. The static configuration in the devicetree assumes that the default WLAN0_WWAN0 is selected; for the other cases we'll still need to fix up things accordingly in the mutable devicetree. Since the chip_info and chip_ops get assigned to the devices below the chip, a generic dummy device is added for each chip. In order for the runtime power management of the NVMe SSDs to work, the NVMe PCIe devices behind external PCIe port bridges need to be below a drivers/pcie/rtd3/device chip entry. Those chips and devices below the bridges to the external PCIe ports are independent of each other; the MPIO chip has the info used for the MPIO lane and engine configuration for the PCIe port on the host side while the rtd3 chip has the info that gets attached to the device behind that bridge. [TODO] Still need to figure out which value needs to be assigned to the gpio_group struct element. I'd expect this to be GPIO_26, but still need to verify this. Also the WLAN01 and WWAN01 cases need to be handled, but that's probably something for a follow-up patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb --- M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb 1 file changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/81101/1 diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index 58cead5..aaccc8b 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -44,7 +44,25 @@ device domain 0 on device ref iommu on end device ref gpp_bridge_1_1 on end # MXM + chip vendorcode/amd/opensil/stub/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "0" + register "end_lane" = "7" + register "gpio_group" = "1" # TODO + register "aspm" = "ASPM_L1" + register "clk_req" = "CLK_REQ0" + device generic 0 on end # dummy for configuring mpio + end device ref gpp_bridge_1_2 on + chip vendorcode/amd/opensil/stub/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "8" + register "end_lane" = "11" + register "gpio_group" = "1" # TODO + register "aspm" = "ASPM_L1" + register "clk_req" = "CLK_REQ1" + device generic 0 on end + end # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device register "name" = ""NVME"" @@ -52,10 +70,55 @@ end end # NVMe SSD1 device ref gpp_bridge_1_3 on end # GBE + chip vendorcode/amd/opensil/stub/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "12" + register "end_lane" = "12" + register "gpio_group" = "1" # TODO + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ6" + device generic 0 on end + end device ref gpp_bridge_2_1 on end # SD + chip vendorcode/amd/opensil/stub/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "13" + register "end_lane" = "13" + register "gpio_group" = "1" # TODO + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ5" + device generic 0 on end + end device ref gpp_bridge_2_2 on end # WWAN + chip vendorcode/amd/opensil/stub/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "14" + register "end_lane" = "14" + register "gpio_group" = "1" # TODO + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ4" + device generic 0 on end + end device ref gpp_bridge_2_3 on end # WIFI + chip vendorcode/amd/opensil/stub/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "15" + register "end_lane" = "15" + register "gpio_group" = "1" # TODO + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ3" + device generic 0 on end + end device ref gpp_bridge_2_4 on + chip vendorcode/amd/opensil/stub/mpio + register "type" = "ENGINE_PCIE" + register "start_lane" = "16" + register "end_lane" = "19" + register "gpio_group" = "1" # TODO + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ2" + device generic 0 on end + end # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device register "name" = ""NVME"" -- To view, visit https://review.coreboot.org/c/coreboot/+/81101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb Gerrit-Change-Number: 81101 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: vc/amd/opensil/stub: add stub MPIO driver
by Felix Held (Code Review) 06 Mar '24

06 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81100?usp=email ) Change subject: vc/amd/opensil/stub: add stub MPIO driver ...................................................................... vc/amd/opensil/stub: add stub MPIO driver Add a stub MPIO chip driver to the openSIL stub code, so that the devicetree entries needed for the MPIO chip can already be added to the mainboard's devicetree files. This driver won't do anything, but still allows the register settings in the devicetree to be set to make switching over to the actual openSIL code and the corresponding glue code easier. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e --- M src/vendorcode/amd/opensil/stub/Makefile.mk A src/vendorcode/amd/opensil/stub/mpio/Makefile.mk A src/vendorcode/amd/opensil/stub/mpio/chip.c A src/vendorcode/amd/opensil/stub/mpio/chip.h 4 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/81100/1 diff --git a/src/vendorcode/amd/opensil/stub/Makefile.mk b/src/vendorcode/amd/opensil/stub/Makefile.mk index 29ef421..299844d 100644 --- a/src/vendorcode/amd/opensil/stub/Makefile.mk +++ b/src/vendorcode/amd/opensil/stub/Makefile.mk @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +subdirs-y += mpio + romstage-y += romstage.c ramstage-y += ramstage.c \ No newline at end of file diff --git a/src/vendorcode/amd/opensil/stub/mpio/Makefile.mk b/src/vendorcode/amd/opensil/stub/mpio/Makefile.mk new file mode 100644 index 0000000..a8d8592 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/mpio/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += chip.c diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.c b/src/vendorcode/amd/opensil/stub/mpio/chip.c new file mode 100644 index 0000000..895814d --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations vendorcode_amd_opensil_stub_mpio_ops = { + .name = "AMD openSIL stub MPIO", +}; diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.h b/src/vendorcode/amd/opensil/stub/mpio/chip.h new file mode 100644 index 0000000..53d22a0 --- /dev/null +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> + +enum mpio_engine_type { + ENGINE_PCIE, + ENGINE_SATA, +}; + +/* Sync with PCIE_HOTPLUG_TYPE */ +enum mpio_hotplug { + HOTPLUG_DISABLED = 0, + HOTPLUG_BASIC, + HOTPLUG_SERVER_EXPRESS, + HOTPLUG_ENHANCED, + HOTPLUG_INBOARD, + HOTPLUG_SERVER_ENT_SSD, + HOTPLUG_UBM, + HOTPLUG_OCP, +}; + +enum pcie_link_speed { + GEN_MAX = 0, /* Maximum supported */ + GEN1, + GEN2, + GEN3, + GEN4, + GEN5, +}; + +/* Sync with PCIE_ASPM_TYPE */ +enum pcie_aspm { + ASPM_DISABLED = 0, + ASPM_L0s, + ASPM_L1, + ASPM_L0sL1, +}; + + +/* CLKREQ for PCIe type descriptors */ +enum pcie_clk_req { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4, + CLK_REQ5, + CLK_REQ6, +}; + +enum pcie_slot_power_limit_scale { + SLOT_POWER_LIMIT_DIVISOR_1 = 0, /* Scale factor 1 */ + SLOT_POWER_LIMIT_DIVISOR_10 = 1, /* Scale factor 0.1 */ + SLOT_POWER_LIMIT_DIVISOR_100 = 2, /* Scale factor 0.01 */ + SLOT_POWER_LIMIT_DIVISOR_1000 = 3, /* Scale factor 0.001 */ +}; + +struct vendorcode_amd_opensil_stub_mpio_config { + enum mpio_engine_type type; + uint8_t start_lane; + uint8_t end_lane; + uint8_t gpio_group; + enum mpio_hotplug hotplug; + enum pcie_link_speed speed_capability; + enum pcie_aspm aspm; + bool aspm_l1_1; + bool aspm_l1_2; + enum pcie_clk_req clk_req; + bool clock_pm; + uint8_t slot_power_limit; + enum pcie_slot_power_limit_scale slot_power_limit_scale; + bool bmc; +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/81100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e Gerrit-Change-Number: 81100 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains
by Shuo Liu (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email ) Change subject: soc/intel/xeon_sp: Create CXL domains ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This is a prototype, but I hope this can help https://review.coreboot.org/c/coreboot/+/80796 since the CRS sharing is the right direction. Look for suggestions. -- To view, visit https://review.coreboot.org/c/coreboot/+/81099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Gerrit-Change-Number: 81099 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 06 Mar 2024 15:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains
by Shuo Liu (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email ) Change subject: soc/intel/xeon_sp: Create CXL domains ...................................................................... soc/intel/xeon_sp: Create CXL domains TEST=intel/archercity CRB P.S. The SUT is not with CXL cards however we hope this refactor could be integrated first as an improvement of the design. Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 2 files changed, 80 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/81099/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 8060e2a..5ac886c 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -148,6 +148,41 @@ } } +void iio_cxl_domain_read_resources(struct device *dev) +{ + struct resource *res; + const STACK_RES *sr = domain_to_stack_res(dev); + + if (!sr) + return; + + int index = 0; + + if (sr->IoBase < sr->PciResourceIoBase) { + res = new_resource(dev, index++); + res->base = sr->IoBase; + res->limit = sr->PciResourceIoBase - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + } + + if (sr->Mmio32Base < sr->PciResourceMem32Base) { + res = new_resource(dev, index++); + res->base = sr->Mmio32Base; + res->limit = sr->PciResourceMem32Base - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } + + if (sr->Mmio64Base < sr->PciResourceMem64Base) { + res = new_resource(dev, index++); + res->base = sr->Mmio64Base; + res->limit = sr->PciResourceMem64Base - 1; + res->size = res->limit - res->base + 1; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + } +} + /* * Used by IIO stacks for PCIe bridges. Those contain 1 PCI host bridges, * all the bus numbers on the IIO stack can be used for this bridge @@ -171,6 +206,15 @@ #endif }; +static struct device_operations iio_cxl_domain_ops = { + .read_resources = iio_cxl_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, +#endif +}; + /* * Used by UBOX stacks. Those contain multiple PCI host bridges, each having * only one bus with UBOX devices. UBOX devices have no resources. @@ -184,13 +228,14 @@ #endif }; -static void soc_create_pcie_domains(const union xeon_domain_path dp, struct bus *upstream, - const STACK_RES *sr) +static void soc_create_domains(const union xeon_domain_path dp, struct bus *upstream, + int bus_base, int bus_limit, const char *type, + struct device_operations *ops) { union xeon_domain_path new_path = { .domain_path = dp.domain_path }; - new_path.bus = sr->BusBase; + new_path.bus = bus_base; struct device_path path = { .type = DEVICE_PATH_DOMAIN, @@ -203,13 +248,31 @@ if (!domain) die("%s: out of memory.\n", __func__); - domain->ops = &iio_pcie_domain_ops; - iio_domain_set_acpi_name(domain, DOMAIN_TYPE_PCIE); + domain->ops = ops; + iio_domain_set_acpi_name(domain, type); struct bus *const bus = alloc_bus(domain); - bus->secondary = sr->BusBase; - bus->subordinate = sr->BusBase; - bus->max_subordinate = sr->BusLimit; + bus->secondary = bus_base; + bus->subordinate = bus_base; + bus->max_subordinate = bus_limit; +} + + +static void soc_create_pcie_domains(const union xeon_domain_path dp, struct bus *upstream, + const STACK_RES *sr) +{ + soc_create_domains(dp, upstream, sr->BusBase, sr->BusLimit, DOMAIN_TYPE_PCIE, + &iio_pcie_domain_ops); +} + +static void soc_create_cxl_domains(const union xeon_domain_path dp, struct bus *upstream, + const STACK_RES *sr) +{ + assert(sr->BusBase + 1 <= sr->BusLimit); + soc_create_domains(dp, upstream, sr->BusBase, sr->BusBase, DOMAIN_TYPE_PCIE, + &iio_cxl_domain_ops); + soc_create_domains(dp, upstream, sr->BusBase + 1, sr->BusLimit, DOMAIN_TYPE_CXL, + &iio_cxl_domain_ops); } /* @@ -220,36 +283,13 @@ static void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus *upstream, const STACK_RES *sr) { - union xeon_domain_path new_path = { - .domain_path = dp.domain_path - }; - /* Only expect 2 UBOX buses here */ - int bus_base = sr->BusBase; - int bus_limit = sr->BusLimit; - assert(bus_base + 1 == bus_limit); - for (int i = bus_base; i <= bus_limit; i++) { - new_path.bus = i; + assert(sr->BusBase + 1 == sr->BusLimit); - struct device_path path = { - .type = DEVICE_PATH_DOMAIN, - .domain = { - .domain = new_path.domain_path, - }, - }; - struct device *const domain = alloc_find_dev(upstream, &path); - if (!domain) - die("%s: out of memory.\n", __func__); - - domain->ops = &ubox_pcie_domain_ops; - const char *prefix = (i == bus_base) ? DOMAIN_TYPE_UBX0 : DOMAIN_TYPE_UBX1; - iio_domain_set_acpi_name(domain, prefix); - - struct bus *const bus = alloc_bus(domain); - bus->secondary = i; - bus->subordinate = bus->secondary; - bus->max_subordinate = bus->secondary; - } + soc_create_domains(dp, upstream, sr->BusBase, sr->BusBase, DOMAIN_TYPE_UBX0, + &ubox_pcie_domain_ops); + soc_create_domains(dp, upstream, sr->BusLimit, sr->BusLimit, DOMAIN_TYPE_UBX1, + &ubox_pcie_domain_ops); } /* Attach stack as domains */ @@ -273,6 +313,8 @@ if (is_ubox_stack_res(ri)) soc_create_ubox_domains(dn, root_bus, ri); + else if (CONFIG(SOC_INTEL_HAS_CXL) && is_iio_cxl_stack_res(ri)) + soc_create_cxl_domains(dn, root_bus, ri); else if (is_pcie_iio_stack_res(ri)) soc_create_pcie_domains(dn, root_bus, ri); else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 47dea8e..ab9b61a 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -28,8 +28,10 @@ #define DOMAIN_TYPE_PCIE "PC" #define DOMAIN_TYPE_UBX0 "UC" #define DOMAIN_TYPE_UBX1 "UD" +#define DOMAIN_TYPE_CXL "CX" void iio_pci_domain_read_resources(struct device *dev); +void iio_cxl_domain_read_resources(struct device *dev); void attach_iio_stacks(void); void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const STACK_RES *sr); -- To view, visit https://review.coreboot.org/c/coreboot/+/81099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Gerrit-Change-Number: 81099 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81098?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overridden. Additionally, the assumption of socket0/stack0 is a PCIe stack is not always true for future generation SoCs and hence this assumption is removed. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ioat.c 6 files changed, 76 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/81098/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Share numa.c among Xeon-SP platforms
by Patrick Rudolph (Code Review) 06 Mar '24

06 Mar '24

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Patrick Rudolph (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email ) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... Patch Set 2: (3 comments) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81098/comment/d3287f54_d2b83609 : PS2, Line 170: northbridge_write_acpi_tables Can this be merged into iio_pcie_domain_ops? You could check in northbridge_write_acpi_tables() if the dev->path is domain 0 and return if not. That would result in even less code. https://review.coreboot.org/c/coreboot/+/81098/comment/57c0925a_602393b6 : PS2, Line 198: domain maybe you can set .bus, .stack and .socket here from the passed arguments to drop the lines above. That would make it easier to read. Technically it would be the same, but you get rid of the new union. https://review.coreboot.org/c/coreboot/+/81098/comment/274aaa77_049a9f7b : PS2, Line 287: downstream dev->path.domain.domain == 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 06 Mar 2024 15:53:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81098?usp=email to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overridden. Additionally, the assumption of socket0/stack0 is a PCIe stack is not always true for future generation SoCs and hence this assumption is removed. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ioat.c 6 files changed, 74 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/81098/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP
by Shuo Liu (Code Review) 06 Mar '24

06 Mar '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81098?usp=email ) Change subject: soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP ...................................................................... soc/intel/xeon_sp: Further share domain creation logics in Xeon-SP With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overriden. Additionally, the assumption of socket0/stack0 is a PCIe stack is not always true for future generation SoCs and hence this assumption is removed. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ioat.c 6 files changed, 74 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/81098/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 03ae70a..6645555 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -148,22 +148,6 @@ } } -void iio_pci_domain_scan_bus(struct device *dev) -{ - const STACK_RES *sr = domain_to_stack_res(dev); - if (!sr) - return; - - struct bus *bus = alloc_bus(dev); - bus->secondary = sr->BusBase; - bus->subordinate = sr->BusBase; - bus->max_subordinate = sr->BusLimit; - - printk(BIOS_SPEW, "Scanning IIO stack %d: busses %x-%x\n", dev->path.domain.domain, - dev->downstream->secondary, dev->downstream->max_subordinate); - pci_host_bridge_scan_bus(dev); -} - /* * Used by IIO stacks for PCIe bridges. Those contain 1 PCI host bridges, * all the bus numbers on the IIO stack can be used for this bridge @@ -171,12 +155,22 @@ static struct device_operations iio_pcie_domain_ops = { .read_resources = iio_pci_domain_read_resources, .set_resources = pci_domain_set_resources, - .scan_bus = iio_pci_domain_scan_bus, + .scan_bus = pci_host_bridge_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = soc_acpi_name, #endif }; +static struct device_operations iio_domain0_ops = { + .read_resources = iio_pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = soc_acpi_name, + .write_acpi_tables = northbridge_write_acpi_tables, +#endif +}; + /* * Used by UBOX stacks. Those contain multiple PCI host bridges, each having * only one bus with UBOX devices. UBOX devices have no resources. @@ -190,19 +184,49 @@ #endif }; +static void soc_create_pcie_domains(const union xeon_domain_path dp, struct bus *upstream, + const STACK_RES *sr) +{ + union xeon_domain_path new_path = { + .domain_path = dp.domain_path + }; + new_path.bus = sr->BusBase; + + struct device_path path = { + .type = DEVICE_PATH_DOMAIN, + .domain = { + .domain = new_path.domain_path, + }, + }; + + struct device *const domain = alloc_find_dev(upstream, &path); + if (!domain) + die("%s: out of memory.\n", __func__); + + domain->ops = &iio_pcie_domain_ops; + iio_domain_set_acpi_name(domain, DOMAIN_TYPE_PCIE); + + struct bus *const bus = alloc_bus(domain); + bus->secondary = sr->BusBase; + bus->subordinate = sr->BusBase; + bus->max_subordinate = sr->BusLimit; +} + /* * On the first Xeon-SP generations there are no separate UBOX stacks, * and the UBOX devices reside on the first and second IIO. Starting * with 3rd gen Xeon-SP the UBOX devices are located on their own IIO. */ static void soc_create_ubox_domains(const union xeon_domain_path dp, struct bus *upstream, - const unsigned int bus_base, const unsigned int bus_limit) + const STACK_RES *sr) { union xeon_domain_path new_path = { .domain_path = dp.domain_path }; /* Only expect 2 UBOX buses here */ + int bus_base = sr->BusBase; + int bus_limit = sr->BusLimit; assert(bus_base + 1 == bus_limit); for (int i = bus_base; i <= bus_limit; i++) { new_path.bus = i; @@ -213,7 +237,7 @@ .domain = new_path.domain_path, }, }; - struct device *const domain = alloc_dev(upstream, &path); + struct device *const domain = alloc_find_dev(upstream, &path); if (!domain) die("%s: out of memory.\n", __func__); @@ -229,19 +253,16 @@ } /* Attach stack as domains */ -void attach_iio_stacks(struct device *dev) +void attach_iio_stacks(void) { const IIO_UDS *hob = get_iio_uds(); union xeon_domain_path dn = { .domain_path = 0 }; if (!hob) return; + struct bus *root_bus = dev_root.downstream; for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { - if (s == 0 && x == 0) { - iio_domain_set_acpi_name(dev, DOMAIN_TYPE_PCIE); - continue; - } const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; if (ri->BusBase > ri->BusLimit) continue; @@ -249,22 +270,24 @@ /* Prepare domain path */ dn.socket = s; dn.stack = x; - dn.bus = ri->BusBase; if (is_ubox_stack_res(ri)) { - soc_create_ubox_domains(dn, dev->upstream, ri->BusBase, ri->BusLimit); + soc_create_ubox_domains(dn, root_bus, ri); } else if (is_pcie_iio_stack_res(ri)) { - struct device_path path; - path.type = DEVICE_PATH_DOMAIN; - path.domain.domain = dn.domain_path; - struct device *iio_domain = alloc_dev(dev->upstream, &path); - if (iio_domain == NULL) - die("%s: out of memory.\n", __func__); - - iio_domain->ops = &iio_pcie_domain_ops; - iio_domain_set_acpi_name(iio_domain, DOMAIN_TYPE_PCIE); - } else if (CONFIG(HAVE_IOAT_DOMAINS)) - soc_create_ioat_domains(dn, dev->upstream, ri); + soc_create_pcie_domains(dn, root_bus, ri); + } else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) + soc_create_ioat_domains(dn, root_bus, ri); } } + +#if CONFIG(HAVE_ACPI_TABLES) + /* rebind domain0 ops for uncore ACPI table writes */ + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN))) { + if (dev->downstream->secondary == 0 && dev->downstream->segment_group == 0) { + dev->ops = &iio_domain0_ops; + break; + } + } +#endif } diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 5fc90e7..8a828c6 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -27,16 +27,6 @@ mainboard_silicon_init_params(silupd); } -static struct device_operations pci_domain_ops = { - .read_resources = iio_pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = iio_pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, - .acpi_name = soc_acpi_name, -#endif -}; - static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, @@ -52,8 +42,7 @@ { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - attach_iio_stacks(dev); + /* domain ops are assigned at their creation */ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } else if (dev->path.type == DEVICE_PATH_GPIO) { @@ -176,6 +165,9 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + + attach_iio_stacks(); + override_hpet_ioapic_bdf(); pch_enable_ioapic(); pch_lock_dmictl(); diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index a010bd1..47dea8e 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -30,8 +30,7 @@ #define DOMAIN_TYPE_UBX1 "UD" void iio_pci_domain_read_resources(struct device *dev); -void iio_pci_domain_scan_bus(struct device *dev); -void attach_iio_stacks(struct device *dev); +void attach_iio_stacks(void); void soc_create_ioat_domains(union xeon_domain_path path, struct bus *bus, const STACK_RES *sr); struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device); diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 92663d9..1911e06 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -13,16 +13,6 @@ #include <soc/soc_util.h> #include <soc/util.h> -static struct device_operations pci_domain_ops = { - .read_resources = iio_pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = iio_pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, - .acpi_name = soc_acpi_name, -#endif -}; - static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, @@ -37,8 +27,7 @@ { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - attach_iio_stacks(dev); + /* domain ops are assigned at their creation */ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } else if (dev->path.type == DEVICE_PATH_GPIO) { @@ -50,6 +39,9 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + + attach_iio_stacks(); + override_hpet_ioapic_bdf(); pch_lock_dmictl(); } diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index cc3719d..a9387f4 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -38,17 +38,6 @@ mainboard_silicon_init_params(silupd); } - -static struct device_operations pci_domain_ops = { - .read_resources = iio_pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = iio_pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, - .acpi_name = soc_acpi_name, -#endif -}; - static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, @@ -64,8 +53,7 @@ { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - attach_iio_stacks(dev); + /* domain ops are assigned at their creation */ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } else if (dev->path.type == DEVICE_PATH_GPIO) { @@ -138,6 +126,9 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + + attach_iio_stacks(); + override_hpet_ioapic_bdf(); pch_enable_ioapic(); pch_lock_dmictl(); diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 5528efa..d944976 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -45,7 +45,7 @@ .domain = new_path.domain_path, }, }; - struct device *const domain = alloc_dev(upstream, &path); + struct device *const domain = alloc_find_dev(upstream, &path); if (!domain) die("%s: out of memory.\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/81098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Gerrit-Change-Number: 81098 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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