Attention is currently required from: Arthur Heymans, Philipp Hug, Xiang W, ron minnich.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email )
Change subject: arch/riscv: Add SMP support for exception handler
......................................................................
Patch Set 8:
(1 comment)
File src/arch/riscv/trap_util.S:
https://review.coreboot.org/c/coreboot/+/68841/comment/f20d1a5e_7e32bbb6 :
PS6, Line 122: jal trap_handler
> change this to: […]
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/68841?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Gerrit-Change-Number: 68841
Gerrit-PatchSet: 8
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: Xiang W <wxjstz(a)126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-Attention: Philipp Hug <philipp(a)hug.cx>
Gerrit-Attention: Xiang W <wxjstz(a)126.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-Comment-Date: Wed, 06 Mar 2024 14:57:23 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx>
Gerrit-MessageType: comment
Attention is currently required from: Arthur Heymans, Xiang W, ron minnich.
Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email )
Change subject: arch/riscv: Add SMP support for exception handler
......................................................................
Patch Set 8:
(5 comments)
File src/arch/riscv/payload.c:
https://review.coreboot.org/c/coreboot/+/68841/comment/34f6d4da_4d63e143 :
PS2, Line 70: write_csr(mscratch, MACHINE_STACK_TOP());
> maybe mention why we save it in a comment. […]
Done
File src/arch/riscv/trap_util.S:
https://review.coreboot.org/c/coreboot/+/68841/comment/d6dd5460_b6a1624f :
PS1, Line 118: bnez sp, 1f
> maybe add the same comment as above for more clarity while reading: […]
Done
File src/arch/riscv/trap_util.S:
https://review.coreboot.org/c/coreboot/+/68841/comment/4ab6d99d_727ca63f :
PS2, Line 12: LOAD x3, 3 * REGBYTES(sp)
> might be worth to note (in a comment) that x2 is the stack pointer otherwise it is not clear why we […]
Done
https://review.coreboot.org/c/coreboot/+/68841/comment/ece46dea_94257f94 :
PS2, Line 103: # when exiting coreboot, write sp to mscratch
> how do we make sure that nothing else writes to MACHINE_TOP_STACK after coreboot is jumping to paylo […]
we would need to setup a PMP region for the stack (and also for the code used inside the trap handler) to protect it from being used by an s-mode payload. Leave that for another day
https://review.coreboot.org/c/coreboot/+/68841/comment/8861b4b9_328ebbd9 :
PS2, Line 105: bnez sp, 1f # sp == 0, trap come from current program
> nit: […]
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/68841?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Gerrit-Change-Number: 68841
Gerrit-PatchSet: 8
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: Xiang W <wxjstz(a)126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-Attention: Xiang W <wxjstz(a)126.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-Comment-Date: Wed, 06 Mar 2024 14:57:10 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-MessageType: comment
Attention is currently required from: Felix Held.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81095?usp=email )
Change subject: mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/81095?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff
Gerrit-Change-Number: 81095
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Wed, 06 Mar 2024 14:56:10 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Felix Held.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81095?usp=email )
Change subject: mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/81095?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff
Gerrit-Change-Number: 81095
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Wed, 06 Mar 2024 14:55:55 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Arthur Heymans, Maximilian Brune, Xiang W, ron minnich.
Maximilian Brune has uploaded a new patch set (#8) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email )
Change subject: arch/riscv: Add SMP support for exception handler
......................................................................
arch/riscv: Add SMP support for exception handler
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M src/arch/riscv/payload.c
M src/arch/riscv/trap_util.S
2 files changed, 117 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68841/8
--
To view, visit https://review.coreboot.org/c/coreboot/+/68841?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Gerrit-Change-Number: 68841
Gerrit-PatchSet: 8
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: Xiang W <wxjstz(a)126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-Attention: Xiang W <wxjstz(a)126.com>
Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Philipp Hug, ron minnich.
Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81082?usp=email )
Change subject: Add weak function for SMP hart count
......................................................................
Add weak function for SMP hart count
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587
---
M src/arch/riscv/include/arch/smp/smp.h
M src/arch/riscv/smp.c
2 files changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81082/1
diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h
index 9d3ae5f..758c4de 100644
--- a/src/arch/riscv/include/arch/smp/smp.h
+++ b/src/arch/riscv/include/arch/smp/smp.h
@@ -3,6 +3,8 @@
#ifndef _RISCV_SMP_H
#define _RISCV_SMP_H
+unsigned int smp_get_hart_count(void);
+
/*
* This function is used to pause smp. Only the hart with hartid equal
* to working_hartid can be returned from smp_pause, other harts will
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index 0a93763..6ecfbc5 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -6,6 +6,12 @@
#include <arch/smp/atomic.h>
#include <console/console.h>
#include <mcall.h>
+#include <assert.h>
+
+__weak unsigned int smp_get_hart_count(void)
+{
+ return CONFIG_MAX_CPUS;
+}
void smp_pause(int working_hartid)
{
@@ -38,10 +44,13 @@
atomic_set(&SYNCB, 0);
atomic_set(&SYNCA, 0x01234567);
- /* waiting for other Hart to enter the halt */
+ int hart_count = smp_get_hart_count();
+ /* waiting for other Hart to enter the halt
+ * use a poor mans timeout to not wait indefinitiely
+ */
do {
barrier();
- } while (atomic_read(&SYNCB) + 1 < CONFIG_MAX_CPUS);
+ } while (atomic_read(&SYNCB) + 1 < hart_count);
/* initialize for the next call */
atomic_set(&SYNCA, 0);
@@ -54,16 +63,17 @@
void smp_resume(void (*fn)(void *), void *arg)
{
int hartid = read_csr(mhartid);
+ int hart_count = smp_get_hart_count();
if (fn == NULL)
die("must pass a non-null function pointer\n");
- for (int i = 0; i < CONFIG_MAX_CPUS; i++) {
+ for (int i = 0; i < hart_count; i++) {
OTHER_HLS(i)->entry.fn = fn;
OTHER_HLS(i)->entry.arg = arg;
}
- for (int i = 0; i < CONFIG_MAX_CPUS; i++)
+ for (int i = 0; i < hart_count; i++)
if (i != hartid)
set_msip(i, 1);
--
To view, visit https://review.coreboot.org/c/coreboot/+/81082?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Icc53185991fed4dbed032a52e51ff71d085ad587
Gerrit-Change-Number: 81082
Gerrit-PatchSet: 1
Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-Attention: Philipp Hug <philipp(a)hug.cx>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-MessageType: newchange
Attention is currently required from: Arthur Heymans, Maximilian Brune, ron minnich.
Maximilian Brune has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: arch/riscv: Add SMP support for exception handler
......................................................................
arch/riscv: Add SMP support for exception handler
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M src/arch/riscv/payload.c
M src/arch/riscv/trap_util.S
2 files changed, 117 insertions(+), 113 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68841/7
--
To view, visit https://review.coreboot.org/c/coreboot/+/68841?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Gerrit-Change-Number: 68841
Gerrit-PatchSet: 7
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-CC: Xiang W <wxjstz(a)126.com>
Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-MessageType: newpatchset