coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: arch/riscv: Makefile.mk: Fix incorrect config variable
by ron minnich (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug, ron minnich. Hello Arthur Heymans, Felix Singer, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81086?usp=email to look at the new patch set (#2). Change subject: arch/riscv: Makefile.mk: Fix incorrect config variable ...................................................................... arch/riscv: Makefile.mk: Fix incorrect config variable ARCH_RISCV_PMP should be CONFIG_ARCH_RISCV_PMP. Rename it. Change-Id: I2a22acae5cd9f30e01c491653bf7fc7b7765d815 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/81086/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a22acae5cd9f30e01c491653bf7fc7b7765d815 Gerrit-Change-Number: 81086 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#4). Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 4 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#3). Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81090?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 2 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: tests: Add `DEBUG` make commandline option to generate debug symbols
by Julius Werner (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Yu-Ping Wu. Hello Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81112?usp=email to review the following change. Change subject: tests: Add `DEBUG` make commandline option to generate debug symbols ...................................................................... tests: Add `DEBUG` make commandline option to generate debug symbols Sometimes when a test doesn't work it's convenient to run it through GDB. This patch adds a variable you can set on the make commandline to conveniently enable all the compiler flags needed to make that work. Change-Id: I3ac80ad095e0b72cc3176cbf915d1f390cd01558 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/tests/Makefile.mk M tests/Makefile.common 2 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81112/1 diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk index e271a7c..9bac9e6 100644 --- a/payloads/libpayload/tests/Makefile.mk +++ b/payloads/libpayload/tests/Makefile.mk @@ -47,7 +47,13 @@ TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type -TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin + +ifneq ($(filter-out 0,$(DEBUG)),) +TEST_CFLAGS += -Og -ggdb3 +else +TEST_CFLAGS += -Os +endif # Make unit-tests detectable by the code TEST_CFLAGS += -D__TEST__ diff --git a/tests/Makefile.common b/tests/Makefile.common index 5cb7b25..ace16d2 100644 --- a/tests/Makefile.common +++ b/tests/Makefile.common @@ -51,7 +51,13 @@ TEST_CFLAGS += -Wno-array-compare -Wno-packed-not-aligned -Wno-trigraphs TEST_CFLAGS += -Wno-unused-but-set-variables -TEST_CFLAGS += -std=gnu11 -Os -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin + +ifneq ($(filter-out 0,$(DEBUG)),) +TEST_CFLAGS += -Og -ggdb3 +else +TEST_CFLAGS += -Os +endif TEST_CFLAGS += -D__TEST__ -- To view, visit https://review.coreboot.org/c/coreboot/+/81112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ac80ad095e0b72cc3176cbf915d1f390cd01558 Gerrit-Change-Number: 81112 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: arch/riscv: Add SMP support for exception handler
by Philipp Hug (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Xiang W. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68841?usp=email ) Change subject: arch/riscv: Add SMP support for exception handler ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Gerrit-Change-Number: 68841 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Xiang W <wxjstz(a)126.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 06 Mar 2024 22:23:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cbfs: Remove broken remnants of PAYLOAD_INFO feature
by Julius Werner (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Julius Werner, Patrick Georgi, ron minnich. Hello Patrick Georgi, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81087?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: cbfs: Remove broken remnants of PAYLOAD_INFO feature ...................................................................... cbfs: Remove broken remnants of PAYLOAD_INFO feature PAYLOAD_INFO is a very old feature that can add a key/value information section to a payload file. It seems to have only ever been generated by coreinfo and never really read by anything. Since CB:1721 in 2012, the feature has been inadvertently broken in practice since the `.note.pinfo` sections that contain the information get discarded from the payload before cbfstool gets to see them. Since CB:28647 in 2018, support for the section in the SELF loader was (inadvertently?) dropped, so if someone actually fed cbfstool a payload ELF that did have a `.note.pinfo` section, modern coreboot would refuse to boot the payload entirely (which is probably not a good state to leave things in). This patch removes the code to generate PAYLOAD_INFO entries entirely, but leaves the support to parse and extract those sections from old payloads in place in cbfstool. Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/coreinfo/Kconfig M payloads/coreinfo/coreinfo.c M payloads/libpayload/include/libpayload.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h M util/cbfstool/cbfs-mkpayload.c M util/cbfstool/cbfs_image.c 6 files changed, 13 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/81087/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81087?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40d8e9b76a171ebcdaa2eae02d54a1ca5e592c85 Gerrit-Change-Number: 81087 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: arch/riscv: use PMP
by ron minnich (Code Review) 06 Mar '24

06 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81090?usp=email ) Change subject: arch/riscv: use PMP ...................................................................... arch/riscv: use PMP With this change, a simple S-mode payload works: 1: li a7, 1 li a0, 48 ecall j 1b Without this change, it will not work. Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/payload.c M src/arch/riscv/pmp.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/81090/1 diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index ee2ee8e..3561171 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cbmem.h> #include <program_loading.h> #include <stdint.h> #include <arch/boot.h> #include <arch/encoding.h> +#include <arch/pmp.h> #include <arch/smp/atomic.h> #include <console/console.h> #include <vm.h> @@ -40,6 +42,7 @@ switch (payload_mode) { case RISCV_PAYLOAD_MODE_S: + setup_pmp(0, (uintptr_t) cbmem_top(), PMP_R|PMP_W|PMP_X); status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S); /* Trap vector base address point to the payload */ write_csr(stvec, doit); diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c index ee39ac4..86a49bb 100644 --- a/src/arch/riscv/pmp.c +++ b/src/arch/riscv/pmp.c @@ -28,6 +28,12 @@ /* This variable is used to record which entries have been used. */ static uintptr_t pmp_entry_used_mask; +/* The architectural spec says that up to 16 PMP entries are available. */ +int pmp_entries_num(void) +{ + return 16; +} + /* helper function used to read pmpcfg[idx] */ static uintptr_t read_pmpcfg(int idx) { -- To view, visit https://review.coreboot.org/c/coreboot/+/81090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7dd171ee69e83f3b904df38c7e2d36cc46a62e Gerrit-Change-Number: 81090 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux
by Won Chung (Code Review) 06 Mar '24

06 Mar '24

Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81089?usp=email ) Change subject: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux ...................................................................... drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux Copy ACPI _PLD values from USB ports to corresponding USB muxes. BUG=to add TEST=emerge coreboot & SSDT dump Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Signed-off-by: Won Chung <wonchung(a)google.com> Tested-by: Emilie Roberts <hadrosaur(a)google.com> --- M src/drivers/intel/pmc_mux/conn/conn.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81089/1 diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index c2c7199..7c58f05 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpigen.h> +#include <acpi/acpi_pld.h> +#include <acpi/acpigen.h> #include <boot/coreboot_tables.h> #include <cbmem.h> #include <console/console.h> @@ -94,12 +96,31 @@ } } +static void get_pld_from_usb_ports(struct acpi_pld *pld, + struct device *usb2_port, struct device *usb3_port) +{ + struct drivers_usb_acpi_config *config = NULL; + + if (usb3_port) + config = usb3_port->chip_info; + else if (usb2_port) + config = usb2_port->chip_info; + + if (config) { + if (config->use_custom_pld) + *pld = config->custom_pld; + else + acpi_pld_fill_usb(pld, config->type, &config->group); + } +} + static void conn_fill_ssdt(const struct device *dev) { struct drivers_intel_pmc_mux_conn_config *config = dev->chip_info; struct acpi_dp *dsd; const char *scope; const char *name; + struct acpi_pld pld = {0}; /* Reference the existing scope and write CONx device */ scope = acpi_device_scope(dev); @@ -131,6 +152,11 @@ acpi_dp_write(dsd); + // Copy _PLD from USB ports + get_pld_from_usb_ports(&pld, config->usb2_port, config->usb3_port); + if (!pld) + acpigen_write_pld(&pld); + acpigen_pop_len(); /* CONx Device */ acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Gerrit-Change-Number: 81089 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Add a new config variable, RISCV_PRIV_VERSION
by ron minnich (Code Review) 06 Mar '24

06 Mar '24

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81088?usp=email ) Change subject: Add a new config variable, RISCV_PRIV_VERSION ...................................................................... Add a new config variable, RISCV_PRIV_VERSION There seems to be no guaranteed way to test this in hardware, so its best to know it at compile time. It should be set in the SoC Kconfig. Change-Id: Ife8d2b70f115c4193b9a8434ebe05893c20224b6 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/81088/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 971dda3..421f3c7 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -110,4 +110,9 @@ config RISCV_WORKING_HARTID int +# Privilege version. There is no default that will work across all +# SoC, so NEVER set a default version here. +config RISCV_PRIV_VERSION + int + endif # if ARCH_RISCV -- To view, visit https://review.coreboot.org/c/coreboot/+/81088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife8d2b70f115c4193b9a8434ebe05893c20224b6 Gerrit-Change-Number: 81088 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2024