coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: amdfwtool: Add functions to link all the tables
by Felix Held (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81252?usp=email ) Change subject: amdfwtool: Add functions to link all the tables ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81252?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieaf97208e943c79d7b76ea62eea9355138c220b9 Gerrit-Change-Number: 81252 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 14:38:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: amdfwtool: Move the address of tables to the context
by Felix Held (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Bao Zheng, Fred Reitberger, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81225?usp=email ) Change subject: amdfwtool: Move the address of tables to the context ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98b7d01e32c75b4f13e23d496cd3de3da900678d Gerrit-Change-Number: 81225 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 14:37:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Patrick Rudolph (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/81316/comment/dcf33a9b_fbd8ba6f : PS5, Line 25: MemoryMapDataHob > used in get_srat_memory_entries How can it be needed when you don't modify any code in uncore_acpi.c? Also there seem to be no common header changes that could explain the change. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 14:32:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/xeon_sp: Initially add IBL codes
by Shuo Liu (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu. Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81315?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/xeon_sp: Initially add IBL codes ...................................................................... soc/xeon_sp: Initially add IBL codes IBL (Integrated Boot Logic) codes are initially forked from EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). Change-Id: I5de2d2f4985b4677dbc156fd8b158c0ab0e46342 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- A src/soc/intel/xeon_sp/ibl/Makefile.mk A src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h A src/soc/intel/xeon_sp/ibl/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/ibl/include/soc/pmc.h A src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h A src/soc/intel/xeon_sp/ibl/include/soc/soc_pm.h A src/soc/intel/xeon_sp/ibl/lockdown.c A src/soc/intel/xeon_sp/ibl/soc_gpio.c A src/soc/intel/xeon_sp/ibl/soc_pch.c A src/soc/intel/xeon_sp/ibl/soc_pmutil.c M src/soc/intel/xeon_sp/include/soc/pch_pci_devs.h 12 files changed, 903 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/81315/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5de2d2f4985b4677dbc156fd8b158c0ab0e46342 Gerrit-Change-Number: 81315 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Redefine data types for FSP2.4 adoption
by Shuo Liu (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81040?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Redefine data types for FSP2.4 adoption ...................................................................... soc/intel/xeon_sp: Redefine data types for FSP2.4 adoption Xeon-SP FSP2.4 introduces UDS_STACK_RES/UDS_SOCKET_RES and retires the usages of STACK_RES/IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both FSP2.4 before and later. Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/include/soc/chip_common.h A src/soc/intel/xeon_sp/include/soc/fsp_adoption.h M src/soc/intel/xeon_sp/include/soc/util.h 5 files changed, 43 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81040/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81040?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Gerrit-Change-Number: 81040 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add GraniteRapids initial codes
by Shuo Liu (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add GraniteRapids initial codes ...................................................................... Patch Set 5: (10 comments) File src/soc/intel/xeon_sp/chip_fsp24.c: https://review.coreboot.org/c/coreboot/+/81316/comment/a4e242fa_db9574c8 : PS5, Line 92: map_uid_to_domain_type > Not needed when the caller passes the correct domain type. Acknowledged https://review.coreboot.org/c/coreboot/+/81316/comment/281bce4e_44bab24e : PS5, Line 95: root > Not needed when PCI root bridges on the same stack do not use overlapping bus ranges. Acknowledged https://review.coreboot.org/c/coreboot/+/81316/comment/75314d75_01730dad : PS5, Line 118: soc_create_fsp24_domains > This is wrong. […] Acknowledged File src/soc/intel/xeon_sp/gnr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/81316/comment/044044f6_5c8a85c7 : PS5, Line 3: acpigen > do you need all those headers? Acknowledged https://review.coreboot.org/c/coreboot/+/81316/comment/2a43fde9_63794536 : PS5, Line 57: uncore_fill_ssdt > removed from main branch Acknowledged File src/soc/intel/xeon_sp/gnr/soc_util.c: https://review.coreboot.org/c/coreboot/+/81316/comment/f6a793c9_1f78bed6 : PS5, Line 127: sizeof > ARRAY_SIZE Acknowledged File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/81316/comment/ec0e78cd_f425e3a7 : PS5, Line 306: ) > soc specific code should be moved out of common code Acknowledged https://review.coreboot.org/c/coreboot/+/81316/comment/45b5ccfa_68769002 : PS5, Line 306: #if CONFIG(PLATFORM_USES_FSP2_4) : int soc_add_dram_resources(struct device *dev, int start_index) : { : return 0; : } : #else > This is wrong and will mess with other resources. Could you please specify? File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/81316/comment/f202b845_579ad153 : PS5, Line 25: MemoryMapDataHob > unrelated? used in get_srat_memory_entries File src/soc/intel/xeon_sp/util.c: https://review.coreboot.org/c/coreboot/+/81316/comment/f21895ac_d30aa9de : PS5, Line 24: unlock_pam_regions > Is it needed at all? I could not figure out what it does or why. Not sure, if SPR pass without this func, do you agree to remove it? -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 14:06:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Update eMMC DLL settings
by Felix Held (Code Review) 19 Mar '24

19 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81304?usp=email ) Change subject: mb/google/nissa/var/craaskov: Update eMMC DLL settings ...................................................................... mb/google/nissa/var/craaskov: Update eMMC DLL settings Update eMMC DLL settings based on Craaskov board. BUG=b:318323026 TEST=executed 2500 cycles of cold boot successfully on all eMMC sku Change-Id: I56f8329c28261c2bcae9d058da929be6763b293c Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81304 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Simon Yang <simon1.yang(a)intel.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/craaskov/overridetree.cb 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Simon Yang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index a070b46..686c829 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -8,6 +8,51 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. # Bit 2 - C1 has a redriver which does SBU muxing. # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. -- To view, visit https://review.coreboot.org/c/coreboot/+/81304?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56f8329c28261c2bcae9d058da929be6763b293c Gerrit-Change-Number: 81304 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz
by Felix Held (Code Review) 19 Mar '24

19 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81136?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz ...................................................................... mb/google/nissa/var/glassway: Tune I2C timings for 400 kHz Update touchpad and touchscreen I2C timing. - Data hold time: 300ns - 900ns BUG=b:328724191 BRANCH=firmware-nissa-15217.B TEST=Check wave form and met the spec. I2C1 (touchscreen) Hold time from 83.58ns to 413.87ns I2C5 (touchpad) Hold time from 95.93ns to 425.27ns Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925 Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81136 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Shawn Ku <shawnku(a)google.com> --- M src/mainboard/google/brya/variants/glassway/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Shawn Ku: Looks good to me, but someone else must approve Martin L Roth: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 8c779d7..29629d4 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -129,7 +129,7 @@ .speed = I2C_SPEED_FAST, .scl_lcnt = 157, .scl_hcnt = 79, - .sda_hold = 7, + .sda_hold = 40, } }, .i2c[2] = { @@ -156,7 +156,7 @@ .speed = I2C_SPEED_FAST, .scl_lcnt = 158, .scl_hcnt = 79, - .sda_hold = 7, + .sda_hold = 40, } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/81136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925 Gerrit-Change-Number: 81136 Gerrit-PatchSet: 13 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Adjust touchscreen power sequencing
by Felix Held (Code Review) 19 Mar '24

19 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81135?usp=email ) Change subject: mb/google/nissa/var/glassway: Adjust touchscreen power sequencing ...................................................................... mb/google/nissa/var/glassway: Adjust touchscreen power sequencing Adjust touchscreen power sequencing for eKTH5015M. The INX touch panel (eKTH5015M) contains a pull-up register which causes TCHSCR_REPORT_EN pull-up abnormally from Z1 power on.Because the t25 must be at least greater than 20ms, TCHSCR_REPORT_EN is initialized to GPO_L in the early stage (romstage) to meet the spec. BUG=b:328170008 BRANCH=firmware-nissa-15217.B TEST=Build and check I2C devices timing meet spec. [INFO ] input: Elan Touchscreen as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-ELAN0001:00/input/in4 Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81135 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/glassway/gpio.c M src/mainboard/google/brya/variants/glassway/overridetree.cb 2 files changed, 6 insertions(+), 4 deletions(-) Approvals: Eric Lai: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/glassway/gpio.c b/src/mainboard/google/brya/variants/glassway/gpio.c index d3510a1..79697d5 100644 --- a/src/mainboard/google/brya/variants/glassway/gpio.c +++ b/src/mainboard/google/brya/variants/glassway/gpio.c @@ -100,6 +100,8 @@ PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C1 : SMBDATA ==> USI_RST_L */ PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C6 : SML1CLK ==> TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), /* H12 : UART0_RTS# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H12, 1, DEEP), }; diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 15b7d7e..8c779d7 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -323,13 +323,13 @@ register "desc" = ""ELAN Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "reset_delay_ms" = "25" + register "reset_delay_ms" = "20" register "reset_off_delay_ms" = "4" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "stop_delay_ms" = "25" - register "stop_off_delay_ms" = "2" + register "stop_delay_ms" = "5" + register "stop_off_delay_ms" = "25" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "enable_delay_ms" = "7" + register "enable_delay_ms" = "25" register "has_power_resource" = "1" device i2c 10 on probe TOUCHSCREEN_SOURCE TOUCHSCREEN_UNPROVISIONED -- To view, visit https://review.coreboot.org/c/coreboot/+/81135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a Gerrit-Change-Number: 81135 Gerrit-PatchSet: 18 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/dptf: Add DCFG method support
by Arthur Heymans (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Eric Lai, Kapil Porwal, Paul Menzel, Sumeet R Pawnikar. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78386?usp=email ) Change subject: drivers/intel/dptf: Add DCFG method support ...................................................................... Patch Set 5: (2 comments) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/78386/comment/730b95f7_163d5fd2 : PS5, Line 162: DPTF copy pasta? https://review.coreboot.org/c/coreboot/+/78386/comment/d45d7ee6_6966ca94 : PS5, Line 164: : acpigen_write_method("DCFG", 0); : acpigen_emit_byte(RETURN_OP); : acpigen_write_integer(config->dcfg); : acpigen_write_method_end(); why not use acpigen_write_name_integer("DCFG", config->dcfg) ? It does not have to be a method afaict. -- To view, visit https://review.coreboot.org/c/coreboot/+/78386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Gerrit-Change-Number: 78386 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 13:13:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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