coreboot-gerrit March 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Shuo Liu (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Ray Ni, Shuo Liu, Tim Chu. Shuo Liu has uploaded a new patch set (#2) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... soc/intel/xeon_sp/spr: Enable x86_64 support Fix compilation errors when compiled for x86_64. TEST=Booted on ibm/sbp1 to linux payload. TEST=intel/archercity CRB Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/romstage.c M src/soc/intel/xeon_sp/spr/upd_display.c M src/soc/intel/xeon_sp/uncore_acpi.c 4 files changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81280/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
by Ashish Kumar Mishra (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Karthik Ramasubramanian, Paul Menzel, Shelley Chen. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81224?usp=email ) Change subject: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81224/comment/7f6e2118_718ad370 : PS3, Line 11: This also adds a warm boot step, only when booting from cold reset : to disable the UFS Controller. > I do not understand the relation regarding to the Kconfig change at hand. […] Choosing this KConfig handles UFS disable on relevant SKUs and it requires a cold reset, during which the settings will be applied and a warm boot triggered. This is added to clarify the behavior expected due to this Kconfig. https://review.coreboot.org/c/coreboot/+/81224/comment/4d047b4c_1340af88 : PS3, Line 9: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig. : This enables a single binary for both SKU1 and SKU2. : This also adds a warm boot step, only when booting from cold reset : to disable the UFS Controller. > Please add a blank line between paragraphs, or do not break lines just because a sentence ends. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Gerrit-Change-Number: 81224 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 11:16:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/Kconfig: Rename FSPRel.bin to FSP.fd
by Mario Scheithauer (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Felix Singer, Lean Sheng Tan, Nico Huber, Paul Menzel, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81344?usp=email ) Change subject: soc/intel/elkhartlake/Kconfig: Rename FSPRel.bin to FSP.fd ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hmmm, the old file is still around and the newer has a different version […] Yes, it is the same code base but with a new label. However, I have no information as to why Intel used the new labelling. But I think that the previous name didn't fit, so it was renamed to FSPRel.bin. -- To view, visit https://review.coreboot.org/c/coreboot/+/81344?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc87ea2744e971d58e9a402f7cf04ef3f316f3b8 Gerrit-Change-Number: 81344 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 11:08:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
by Ashish Kumar Mishra (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian, Shelley Chen. Hello Karthik Ramasubramanian, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81224?usp=email to look at the new patch set (#4). Change subject: mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS ...................................................................... mb/google/brox: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig. This enables a single binary for both SKU1 and SKU2. For SKU2, upon boot from cold reset, it will disable the UFS Controller and then trigger a warm boot. BUG=b:329209576 BRANCH=None TEST=Boot image on SKU1/SKU2 and check S0ix working. Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/81224/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4 Gerrit-Change-Number: 81224 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Drop RMRR entry for USB
by Patrick Rudolph (Code Review) 19 Mar '24

19 Mar '24

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81297?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Drop RMRR entry for USB ...................................................................... soc/intel/xeon_sp: Drop RMRR entry for USB Drop RMRR entry for XHCI controller since it's not under BIOS control. There's no USB-PS/2 emulation done in SMM, hence it's not needed. TEST=intel/archercity CRB Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/uncore_acpi.c 3 files changed, 1 insertion(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 615b8c6..b88a083 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -61,7 +61,7 @@ #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 #define CBMEM_ID_STAGEx_RAW 0x57a9e200 -#define CBMEM_ID_STORAGE_DATA 0x53746f72 +#define CBMEM_ID_STORAGE_DATA 0x53746f72 /* deprecated */ #define CBMEM_ID_TPM_CB_LOG 0x54435041 /* TPM log in coreboot-specific format */ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 /* TPM log per TPM 1.2 specification */ #define CBMEM_ID_TIMESTAMP 0x54494d45 diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 882c226..e374544 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -16,11 +16,6 @@ CSTATES_C1C6 }; -#define MEM_BLK_COUNT 0x140 -typedef struct { - uint8_t buf[32]; -} MEM_BLK; - unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index ef72335..86c3a66 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -439,33 +439,6 @@ static unsigned long acpi_create_rmrr(unsigned long current) { - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - - uint32_t *ptr; - - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr); - memset(ptr, 0, size); - } - - unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t)ptr, (uint32_t)((uint32_t)ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t)ptr, - (uint32_t)((uint32_t)ptr + size - 1)); - - printk(BIOS_DEBUG, " [PCI Endpoint Device] PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", - XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, - PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); - - acpi_dmar_rmrr_fixup(tmp, current); - return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1 Gerrit-Change-Number: 81297 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/Kconfig: Rename FSPRel.bin to FSP.fd
by Nico Huber (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Felix Singer, Lean Sheng Tan, Mario Scheithauer, Paul Menzel, Werner Zeh. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81344?usp=email ) Change subject: soc/intel/elkhartlake/Kconfig: Rename FSPRel.bin to FSP.fd ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hmmm, the old file is still around and the newer has a different version scheme (MR7 vs. IPU2024.2) do we know any details? is this the same line of FSP? -- To view, visit https://review.coreboot.org/c/coreboot/+/81344?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc87ea2744e971d58e9a402f7cf04ef3f316f3b8 Gerrit-Change-Number: 81344 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 10:25:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop uncore_fill_ssdt
by Patrick Rudolph (Code Review) 19 Mar '24

19 Mar '24

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81273?usp=email ) Change subject: soc/intel/xeon_sp: Drop uncore_fill_ssdt ...................................................................... soc/intel/xeon_sp: Drop uncore_fill_ssdt Let ACPI DSDT figure out by itself if a stack is enabled. Allows to drop uncore_fill_ssdt() on all platforms. TEST=intel/archercity CRB Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81273 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c 8 files changed, 25 insertions(+), 83 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index b2d6d79..1434fbf 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -41,10 +41,6 @@ fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); } -void uncore_fill_ssdt(const struct device *device) -{ -} - /* TODO: See if we can use the common generate_p_state_entries */ void soc_power_states_generation(int core, int cores_per_package) { diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index afccfe4..882c226 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -23,7 +23,6 @@ unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void uncore_fill_ssdt(const struct device *device); unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); unsigned long acpi_fill_cedt(unsigned long current); unsigned long acpi_fill_hmat(unsigned long current); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index b98e998..30e14d3 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -54,10 +54,6 @@ fill_fadt_extended_pm_io(fadt); } -void uncore_fill_ssdt(const struct device *device) -{ -} - void soc_power_states_generation(int core, int cores_per_package) { } diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 80b3da2..553ca9d 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -17,10 +17,20 @@ EisaId ("PNP0A03") /* PCI Bus */ }) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) - External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) - Method (_STA, 0, NotSerialized) // _STA: Status + Method (_STA, 0, NotSerialized) { - Return (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) + /* + * _CRS is being generated by SSDT for available stacks only and + * when missing the stack isn't available. + */ + If (CondRefOf (_CRS)) + { + Return (0xf) + } + Else + { + Return (0) + } } Method (_PRT, 0, NotSerialized) { diff --git a/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl index 552f4c0..5c3d7ea 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/iiostack.asl @@ -3,8 +3,6 @@ /* ***** PCI Stacks **** */ #undef DEVPREFIX #define DEVPREFIX PC -#undef STPREFIX -#define STPREFIX ST #undef PRTID #define PRTID AR00 diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index c65b699..fdb599e 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -13,10 +13,20 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) - External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) Method (_STA, 0, NotSerialized) { - Return (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) + /* + * _CRS is being generated by SSDT for available stacks only and + * when missing the stack isn't available. + */ + If (CondRefOf (_CRS)) + { + Return (0xf) + } + Else + { + Return (0) + } } Method (_PRT, 0, NotSerialized) { diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 0b6e491..607ee6c 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -53,70 +53,6 @@ fill_fadt_extended_pm_io(fadt); } -/* - * Add a DSDT ACPI Name field for STACK enable setting. - * This is retrieved by the device _STA defined in iiostack.asl - */ -static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, bool stack_enabled) -{ - char stack_sta[16]; - snprintf(stack_sta, sizeof(stack_sta), "ST%d%X", socket, stack); - - if (!stack_enabled) - acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_OFF); - else - acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_ON); -} - -void uncore_fill_ssdt(const struct device *device) -{ - bool stack_enabled; - - /* Only add RTxx entries once. */ - if (device->upstream->secondary != 0) - return; - - /* - Write stack scope - this needs to match RP ACPI scopes. - Stacks 0 (TYPE_UBOX_IIO) - Scope: PC<socket><stack>, ResourceTemplate: P0RS - Stacks 1 .. 5 (TYPE_UBOX_IIO) - Scope: PC<socket><stack> & CX<socket><stack>, ResourceTemplate: RBRS - Stacks 8 .. B (TYPE_DINO) - Scope: DI<socket><stack> for DINO, ResourceTemplate: RBRS - Scope: CP<socket><stack> for CPM (i.e., QAT), ResourceTemplate: RBRS - Scope: HQ<socket><stack> for HQM (i.e., DLB), ResourceTemplate: RBRS - Stacks D .. E (TYPE_UBOX) - Scope: UC<socket><0..1> for UBOX[1-2], ResourceTemplate: UNRS - */ - - printk(BIOS_DEBUG, "%s device: %s\n", __func__, dev_path(device)); - - /* The _CSR generation must match SPR iiostack.asl. */ - const IIO_UDS *hob = get_iio_uds(); - /* Iterate over CONFIG_MAX_SOCKET to keep ASL templates and DSDT injection in sync */ - for (uint8_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { - for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { - const STACK_RES *ri = - &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - - stack_enabled = soc_cpu_is_enabled(socket) && - ri->Personality < TYPE_RESERVED; - - printk(BIOS_DEBUG, "%s processing socket: %d, stack: %d, type: %d\n", - __func__, socket, stack, ri->Personality); - - if (stack <= IioStack5) { // TYPE_UBOX_IIO - create_dsdt_stack_sta(socket, stack, stack_enabled); - } else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO - create_dsdt_stack_sta(socket, stack, stack_enabled); - } else if (stack == IioStack13) { // TYPE_UBOX - create_dsdt_stack_sta(socket, stack, stack_enabled); - } - } - } -} - /* TODO: See if we can use the common generate_p_state_entries */ void soc_power_states_generation(int core, int cores_per_package) { diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 952ca4d..0eaff06 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -369,9 +369,6 @@ .enable_resources = pci_dev_enable_resources, .init = mmapvtd_init, .ops_pci = &soc_pci_ops, -#if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = uncore_fill_ssdt, -#endif }; static const unsigned short mmapvtd_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/81273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979 Gerrit-Change-Number: 81273 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by default
by Patrick Rudolph (Code Review) 19 Mar '24

19 Mar '24

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81187?usp=email ) Change subject: soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by default ...................................................................... soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by default As of now coreboot only supported one PCI segment group and thus the MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the default FSP doesn't allow to disable unused IIO stacks a patched version had to be used. Those unused IIO stacks consume lots of PCI bus ranges, leaving no free buses for the secondary side behind PCI bridges. The IIO disable mechanism doesn't work after ACPI G3 exit and thus requires multiple reboots when the previous state was G3. Since coreboot now supports multi PCI segment groups enable 512 MMCONF buses on 4S platforms by default and drop the IIO stack disable UPDs on ibm/sbp1. This allows to boot faster without the need for a patched FSP. The use of multiple PCI segment groups might prevent legacy software from working properly, however the only board where multiple PCI segment groups are used uses u-root as default payload. TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups. TEST=intel/archercity CRB Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/ibm/sbp1/romstage.c M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/spr/romstage.c 3 files changed, 30 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c index 5cda689..365d6b1 100644 --- a/src/mainboard/ibm/sbp1/romstage.c +++ b/src/mainboard/ibm/sbp1/romstage.c @@ -270,8 +270,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - UINT32 *sktbmp; - /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; @@ -287,25 +285,7 @@ else mupd->FspmConfig.serialDebugMsgLvl = 0; - /* Force 256MiB MMCONF (Segment0) only */ - mupd->FspmConfig.mmCfgSize = 0x2; mupd->FspmConfig.PcieHotPlugEnable = 1; - - /* - * Disable unused IIO stack: - * Socket 0 : IIO1, IIO4 - * Socket 1 : IIO1, IIO2 - * Socket 2 : IIO1, IIO5 - * Socket 3 : IIO1, IIO5 - * Stack Disable bit mapping is: - * IIO stack number: 1 2 3 4 5 - * Stack Disable Bit: 1 5 3 2 4 - */ - sktbmp = (UINT32 *)&mupd->FspmConfig.StackDisableBitMap[0]; - sktbmp[0] = BIT(1) | BIT(2); - sktbmp[1] = BIT(1) | BIT(5); - sktbmp[2] = BIT(1) | BIT(4); - sktbmp[3] = BIT(1) | BIT(4); soc_config_iio(mupd, sbp1_socket_config, sbp1_socket_config_iou); } diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 52aaec17..923527e3 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -89,6 +89,7 @@ default 0x80000000 config ECAM_MMCONF_BUS_NUMBER + default 512 if MAX_SOCKET = 4 default 256 config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 4cce21f..74976b3 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -211,6 +211,35 @@ m_cfg->mmiohBase = 0x2000; m_cfg->mmiohSize = 0x3; + /* + * By default FSP will set MMCFG size to 256 buses on 1S and 2S platforms + * and 512 buses on 4S platforms. 512 buses are implemented by using multiple + * PCI segment groups and is likely incompatible with legacy software stacks. + */ + switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) { + case 2048: + m_cfg->mmCfgSize = 5; + break; + case 1024: + m_cfg->mmCfgSize = 4; + break; + case 512: + m_cfg->mmCfgSize = 3; + break; + case 256: + m_cfg->mmCfgSize = 2; + break; + case 128: + m_cfg->mmCfgSize = 1; + break; + case 64: + m_cfg->mmCfgSize = 0; + break; + default: + printk(BIOS_ERR, "%s: Unsupported ECAM_MMCONF_BUS_NUMBER = %d\n", + __func__, CONFIG_ECAM_MMCONF_BUS_NUMBER); + } + m_cfg->BoardTypeBitmask = 0x11111133; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/81187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519 Gerrit-Change-Number: 81187 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/dptf: Add DCFG method support
by Sumeet R Pawnikar (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Eric Lai, Kapil Porwal, Paul Menzel, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78386?usp=email ) Change subject: drivers/intel/dptf: Add DCFG method support ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/78386/comment/b69539c2_55841691 : PS4, Line 164: acpigen_write_name("DCFE"); > How to change the DCFE is it is hard code? Should pass by config? ODM/OEM can configure this by adding dcfg config under overridetree.cb file for specific product. Submitted TEST patch https://review.coreboot.org/c/coreboot/+/81345 on usage of this. -- To view, visit https://review.coreboot.org/c/coreboot/+/78386?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Gerrit-Change-Number: 78386 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 19 Mar 2024 10:12:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: TEST: use dcfg config to control thermal tuning mechanism
by Sumeet R Pawnikar (Code Review) 19 Mar '24

19 Mar '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81345?usp=email ) Change subject: TEST: use dcfg config to control thermal tuning mechanism ...................................................................... TEST: use dcfg config to control thermal tuning mechanism This is an example on how to use dcfg config to control the thermal tuning mechanism on specific platform. BUG=b:272382080 TEST=Build, boot on rex board and dump SSDT to check DCFG method. Also, verified the value over sysfs attribute "production_mode" present under /sys/bus/platform/devices/INTC1042:00 path. Change-Id: I12c84d16102c1678c8f0162af15f34587c978028 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/81345/1 diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 12068ce..55e39b2 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -176,6 +176,9 @@ end # Integrated Graphics Device device ref dtt on chip drivers/intel/dptf + + register "dcfg" = "5" + ## sensor information register "options.tsr[0].desc" = ""DDR_SOC"" register "options.tsr[1].desc" = ""Ambient"" -- To view, visit https://review.coreboot.org/c/coreboot/+/81345?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12c84d16102c1678c8f0162af15f34587c978028 Gerrit-Change-Number: 81345 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

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