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Change subject: mb/google/brya: Create yavista variant
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
> I think that can update in following patch.
Acknowledged.
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Change subject: libpayload: Remove legacy CBFS API
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/adl: Set slp-s0 counter frequency
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/lenovo/m900_tiny/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80610/comment/8794d4d7_173ee729 :
PS6, Line 173: device ref uart2 off end # LPSS UART - pins 17, 18 on GXDP header on board underside
> Removed and added a comment to the commit message.
Done
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Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
Patch Set 7:
(10 comments)
File src/mainboard/lenovo/m900_tiny/Kconfig:
https://review.coreboot.org/c/coreboot/+/80610/comment/f1a5da14_9baf20bb :
PS6, Line 25: int
> Remove, avoid type redefinitions.
Done
https://review.coreboot.org/c/coreboot/+/80610/comment/6d452347_1e39f09b :
PS6, Line 36: hex
> Remove, avoid type redefinitions.
Done
File src/mainboard/lenovo/m900_tiny/bootblock.c:
https://review.coreboot.org/c/coreboot/+/80610/comment/6c185968_6fbbeb43 :
PS6, Line 13: void bootblock_mainboard_init(void)
: {
: mainboard_configure_early_gpios();
: }
> Why is that needed? bootblock_mainboard_early_init() should work fine.
Right, moved to `bootblock_mainboard_early_init()`
File src/mainboard/lenovo/m900_tiny/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80610/comment/fa6cb39e_f2b7159d :
PS6, Line 7: register "deep_s3_enable_ac" = "0"
: r
> Remove
Done
https://review.coreboot.org/c/coreboot/+/80610/comment/7ed613ed_bec5847e :
PS6, Line 23: register "PrimaryDisplay" = "Display_iGFX"
> Move into the igpu scope.
Done
https://review.coreboot.org/c/coreboot/+/80610/comment/b4d70e73_d83df76c :
PS6, Line 162: [5] = 0,
> Remove
Done
https://review.coreboot.org/c/coreboot/+/80610/comment/756f0083_ff717977 :
PS6, Line 167: [2] = 0,
: [3] = 0,
: [4] = 0,
:
> Disabled, remove
Done
https://review.coreboot.org/c/coreboot/+/80610/comment/cb739df7_1694154b :
PS6, Line 173: device ref uart2 off end # LPSS UART - pins 17, 18 on GXDP header on board underside
> Please don't add disabled devices to the devicetree. Document the pins in the commit message.
Removed and added a comment to the commit message.
https://review.coreboot.org/c/coreboot/+/80610/comment/6edcce43_cc7c3824 :
PS6, Line 234: device ref p2sb on end
:
> These are enabled in the chipset devicetree. Remove.
Done
File src/mainboard/lenovo/m900_tiny/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/80610/comment/fc44c343_e275486c :
PS6, Line 10: // OEM revision
> Seems superfluous, remove.
Done
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Hello Alexander Couzens, Arthur Heymans, Krystian Hebel, Maciej Pijanowski, Michał Żygowski, Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by Nicholas Sudsgaard, Verified+1 by build bot (Jenkins)
Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151
processors. M700 comes with B150 chipset, M900 comes with Q170 and is
vPro capable.
There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled
in vendor FW, but for now it's not used here.
LPSS UART for debugging is available on pins 17,18 on the underside of
the mainboard, but it is not enabled by default.
Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5
and Windows 11.
Tested and working:
- Serial port (via optional module)
- Rear DisplayPort connectors
- Graphics w/ libgfxinit
- Ethernet
- SATA
- NVMe
- Internal speaker, front combo jack, rear line-out
- Discrete TPM 1.2
- USB ports (Port 1 untested, apparently broken on my unit)
- M.2 2230 Wi-Fi slot (needs ASPM L1s disabled)
- S3 suspend
- ME disable via NVRAM setting
Untested:
- Front mic input
- Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe
Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
A src/mainboard/lenovo/m900_tiny/Kconfig
A src/mainboard/lenovo/m900_tiny/Kconfig.name
A src/mainboard/lenovo/m900_tiny/Makefile.mk
A src/mainboard/lenovo/m900_tiny/acpi/ec.asl
A src/mainboard/lenovo/m900_tiny/acpi/superio.asl
A src/mainboard/lenovo/m900_tiny/board_info.txt
A src/mainboard/lenovo/m900_tiny/bootblock.c
A src/mainboard/lenovo/m900_tiny/cmos.default
A src/mainboard/lenovo/m900_tiny/cmos.layout
A src/mainboard/lenovo/m900_tiny/data.vbt
A src/mainboard/lenovo/m900_tiny/devicetree.cb
A src/mainboard/lenovo/m900_tiny/dsdt.asl
A src/mainboard/lenovo/m900_tiny/gma-mainboard.ads
A src/mainboard/lenovo/m900_tiny/gpio.c
A src/mainboard/lenovo/m900_tiny/gpio_early.c
A src/mainboard/lenovo/m900_tiny/hda_verb.c
A src/mainboard/lenovo/m900_tiny/include/mainboard/gpio.h
A src/mainboard/lenovo/m900_tiny/ramstage.c
A src/mainboard/lenovo/m900_tiny/romstage.c
19 files changed, 861 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/80610/7
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Change subject: util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS8:
> i would have strongly preferred if we waited with this until the release is tested and published. […]
Same as in CB:80606
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Change subject: crossgcc: Upgrade binutils from 2.41 to 2.42
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> i would have strongly preferred if we waited with this until the release is tested and published. […]
Wait a sec. I think there is a misunderstanding. I've merged the patch after the tag was done. The tag gets announced next week and whatever happens on the main branch any new changes to the release need to be cherry-picked onto a release branch.
At the moment our workflow is to do version updates during a short time window after a release was done, which gives about 3 months time to test these changes.
Does that explanation solve your concerns?
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