Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80689?usp=email )
Change subject: mb/google/brox: Disable Early EC Sync
......................................................................
mb/google/brox: Disable Early EC Sync
Early EC Sync does not need to be enabled in coreboot as EFS2 is being
enabled in the EC.
BUG=b:326152804
BRANCH=None
TEST=emerge-brox coreboot
To be tested with EC sync enabled
Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/80689/1
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig
index 007328f..2260fe1 100644
--- a/src/mainboard/google/brox/Kconfig
+++ b/src/mainboard/google/brox/Kconfig
@@ -111,7 +111,6 @@
default "brox" if BOARD_GOOGLE_BROX
config VBOOT
- select VBOOT_EARLY_EC_SYNC
select VBOOT_LID_SWITCH
config DIMM_SPD_SIZE
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Change subject: soc/intel/alderlake: Add kconfig for Twin Lake
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/80688/comment/0eb9b4b8_34925495 :
PS1, Line 113: and SOC_INTEL_ALDERLAKE_PCH_N together
not needed
```
config SOC_INTEL_TWINLAKE
bool
select SOC_INTEL_ALDERLAKE_PCH_N
help
Intel Twinlake support. Mainboards using TWL should select
SOC_INTEL_TWINLAKE.
```
https://review.coreboot.org/c/coreboot/+/80688/comment/3cf24e41_e3e6c349 :
PS1, Line 406: alderlake_n
shouldn't this be `twinlake`
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Change subject: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> This is really ugly & not easy to review .... ! […]
then* flash the board ...
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Change subject: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
This is really ugly & not easy to review .... !
what if you just run this (just copy paste this line and hit enter ):
"git reset --hard origin/main && git pull && git submodule update --init --checkout && make crossgcc-clean && make crossgcc && git checkout 5e8e911b7caee021faff96c4e82a77a42544ea62 && make distclean && make menuconfig && make"
the flash the board and check if it is ok or not.
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Change subject: libpayload: Remove legacy CBFS API
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/lenovo/m900_tiny/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80610/comment/0221e64e_41dfc940 :
PS7, Line 4: register "s0ix_enable" = "0"
> Another one set to 0 ;)
Ah, removed :)
https://review.coreboot.org/c/coreboot/+/80610/comment/bf297e8d_9913e546 :
PS7, Line 192: #register "gen4_dec" = "0x000c0081"
> Are these supposed to be commented out?
Yes, I got these from vendor firmware and kept them for reference, I can remove them, it's no problem.
Removed.
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Hello Alexander Couzens, Arthur Heymans, Felix Singer, Krystian Hebel, Maciej Pijanowski, Michał Żygowski, Nicholas Sudsgaard, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80610?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151
processors. M700 comes with B150 chipset, M900 comes with Q170 and is
vPro capable.
There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled
in vendor FW, but for now it's not used here.
LPSS UART for debugging is available on pins 17,18 on the underside of
the mainboard, but it is not enabled by default.
Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5
and Windows 11.
Tested and working:
- Serial port (via optional module)
- Rear DisplayPort connectors
- Graphics w/ libgfxinit
- Ethernet
- SATA
- NVMe
- Internal speaker, front combo jack, rear line-out
- Discrete TPM 1.2
- USB ports (Port 1 untested, apparently broken on my unit)
- M.2 2230 Wi-Fi slot (needs ASPM L1s disabled)
- S3 suspend
- ME disable via NVRAM setting
Untested:
- Front mic input
- Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe
Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
A src/mainboard/lenovo/m900_tiny/Kconfig
A src/mainboard/lenovo/m900_tiny/Kconfig.name
A src/mainboard/lenovo/m900_tiny/Makefile.mk
A src/mainboard/lenovo/m900_tiny/acpi/ec.asl
A src/mainboard/lenovo/m900_tiny/acpi/superio.asl
A src/mainboard/lenovo/m900_tiny/board_info.txt
A src/mainboard/lenovo/m900_tiny/bootblock.c
A src/mainboard/lenovo/m900_tiny/cmos.default
A src/mainboard/lenovo/m900_tiny/cmos.layout
A src/mainboard/lenovo/m900_tiny/data.vbt
A src/mainboard/lenovo/m900_tiny/devicetree.cb
A src/mainboard/lenovo/m900_tiny/dsdt.asl
A src/mainboard/lenovo/m900_tiny/gma-mainboard.ads
A src/mainboard/lenovo/m900_tiny/gpio.c
A src/mainboard/lenovo/m900_tiny/gpio_early.c
A src/mainboard/lenovo/m900_tiny/hda_verb.c
A src/mainboard/lenovo/m900_tiny/include/mainboard/gpio.h
A src/mainboard/lenovo/m900_tiny/ramstage.c
A src/mainboard/lenovo/m900_tiny/romstage.c
19 files changed, 854 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/80610/8
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Change subject: soc/intel/xeon_sp: Add memory type check utils
......................................................................
Patch Set 3: Code-Review+1
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