Jincheng Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80692?usp=email )
Change subject: drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
......................................................................
drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by default
MRC_CACHE_USING_MRC_VERSION is by default selected when a platform
uses EDK binding >= 202302 even the corresponding FSP doesn't provide
the feature. Deselect the option and leave it to SoC codes to enable it
depending on needs.
Change-Id: Ibae0fef570e0ddbec7c5e9ccd6d6c8f4ad71d17f
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/drivers/mrc_cache/Kconfig
M src/soc/intel/meteorlake/Kconfig
2 files changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/80692/1
diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig
index e12a3a5..aabb4d8 100644
--- a/src/drivers/mrc_cache/Kconfig
+++ b/src/drivers/mrc_cache/Kconfig
@@ -56,7 +56,6 @@
config MRC_CACHE_USING_MRC_VERSION
bool
- default y if UDK_VERSION >= 202302
default n
help
Use the MRC version info from FSP extended header to store the MRC cache data.
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index f732d69..43bb25e 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -38,6 +38,7 @@
select IOAPIC
select MICROCODE_BLOB_UNDISCLOSED
select MP_SERVICES_PPI_V2
+ select MRC_CACHE_USING_MRC_VERSION
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PCIE_CLOCK_CONTROL_THROUGH_P2SB
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Gerrit-Change-Number: 80692
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Hello Felix Held, Paul Menzel, build bot (Jenkins),
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Change subject: superio/ite: Add IT8629E
......................................................................
superio/ite: Add IT8629E
Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/superio/ite/Makefile.mk
A src/superio/ite/it8629e/Kconfig
A src/superio/ite/it8629e/Makefile.mk
A src/superio/ite/it8629e/chip.h
A src/superio/ite/it8629e/it8629e.h
A src/superio/ite/it8629e/superio.c
6 files changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/80344/11
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Change subject: superio/ite: Add IT8629E
......................................................................
Patch Set 10:
(1 comment)
File src/superio/ite/it8629e/Kconfig:
https://review.coreboot.org/c/coreboot/+/80344/comment/99cbc3cf_b461bcd8 :
PS9, Line 3: # Unfortunately, the datasheet for IT8629E is not public . Therefore, we will
: # use the functionally closest chip (i.e. IT8728F) as a reference and try to
: # reverse-engineer where necessary.
:
: # IT8629E seems to be very similar to IT8628E (again, no public datasheets), as
: # the chip id is 0x8628.
> Please remove that from here and add it to the commit message. […]
Done
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Hello Felix Held, Paul Menzel, build bot (Jenkins),
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to look at the new patch set (#10).
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Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins)
Change subject: superio/ite: Add IT8629E
......................................................................
superio/ite: Add IT8629E
Unfortunately, the datasheet for IT8629E is not public . Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/superio/ite/Makefile.mk
A src/superio/ite/it8629e/Kconfig
A src/superio/ite/it8629e/Makefile.mk
A src/superio/ite/it8629e/chip.h
A src/superio/ite/it8629e/it8629e.h
A src/superio/ite/it8629e/superio.c
6 files changed, 111 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/80344/10
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75905?usp=email )
Change subject: Makefile.inc: Compress DSDT file
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75905/comment/a6da4412_806b7a60 :
PS7, Line 7: Compress DSDT file
Maybe mention the algorithm too?
https://review.coreboot.org/c/coreboot/+/75905/comment/47687f20_0fffcdae :
PS7, Line 9: Now
It’d be great if you referenced the commit introducing the feature.
https://review.coreboot.org/c/coreboot/+/75905/comment/04aaaf65_f76b5fff :
PS7, Line 12:
It’d be great, if you added timing and size data.
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Change subject: mb/google/rex/var/screebo: Refactor SSD power sequencing
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Same comments as in https://review.coreboot.org/c/coreboot/+/80663/1.
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Change subject: mb/google/rex/var/karis: Refactor SSD power sequencing
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80663/comment/0d1d5834_bfc8faef :
PS1, Line 8:
It’d be great if you could start by describing the problem.
https://review.coreboot.org/c/coreboot/+/80663/comment/063e1dc0_ae353256 :
PS1, Line 21: removed
remove
https://review.coreboot.org/c/coreboot/+/80663/comment/ad136326_3649c858 :
PS1, Line 21: hence,
Should the comma be before *hence*?
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Hello Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim, build bot (Jenkins),
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Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
......................................................................
drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It support 64-bits FSP but 64-bits support will be provided by
subsequent patch.
Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase. However, since post-codes are in short supply, memory and
silicon multi-phase init share the same post-codes.
[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf
[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-…
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/upd_display.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/tigerlake/fsp_params.c
M util/cbfstool/eventlog.c
13 files changed, 124 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/15
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Change subject: drivers/intel/fsp2_0: Initialize CPUs only when FSP-S has completed
......................................................................
drivers/intel/fsp2_0: Initialize CPUs only when FSP-S has completed
FSP can also make use of Multi-Processor services during its
multi-phase stages. If `USE_INTEL_FSP_MP_INIT' is set and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI' unset coreboot cannot
take MP ownership as FSP-S may still use EDK2 MP services
concurrently.
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/silicon_init.c
1 file changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80691/1
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index e543628..39c3752 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -155,16 +155,12 @@
fsp_debug_after_silicon_init(status);
fsps_return_value_handler(FSP_SILICON_INIT_API, status);
- /* Reinitialize CPUs if FSP-S has done MP Init */
- if (CONFIG(USE_INTEL_FSP_MP_INIT))
- do_mpinit_after_fsp();
-
if (!CONFIG(PLATFORM_USES_FSP2_2))
- return;
+ goto fsp_init_done;
/* Check if SoC user would like to call Multi Phase Init */
if (!fsp_is_multi_phase_init_enabled())
- return;
+ goto fsp_init_done;
/* Call MultiPhaseSiInit */
multi_phase_si_init = (void *)(uintptr_t)(hdr->image_base +
@@ -172,7 +168,7 @@
/* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */
if (multi_phase_si_init == NULL)
- return;
+ goto fsp_init_done;
post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_ENTRY);
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START);
@@ -202,6 +198,11 @@
}
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
+
+fsp_init_done:
+ /* Reinitialize CPUs if FSP-S has done MP Init */
+ if (CONFIG(USE_INTEL_FSP_MP_INIT))
+ do_mpinit_after_fsp();
}
static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused)
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92
Gerrit-Change-Number: 80691
Gerrit-PatchSet: 1
Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>
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