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Change subject: mb/google/nissa/var/glassway: Generate SPD ID for supported memory parts
......................................................................
Patch Set 1: Code-Review+1
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Change subject: mb/google/nissa/var/glassway: Generate SPD ID for supported memory parts
......................................................................
mb/google/nissa/var/glassway: Generate SPD ID for supported memory parts
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
H58G56AK6BX069 2 (0010)
H9JCNNNBK3MLYR-N6E 3 (0011)
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb
Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
M src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
3 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/80686/1
diff --git a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
index eace2e4..b4d82e9 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
@@ -1,5 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
-# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+# Generated by:
+# /tmp/go-build472300524/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
-SPD_SOURCES = placeholder
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT
+SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069
+SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 3(0b0011) Parts = H9JCNNNBK3MLYR-N6E
diff --git a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
index fa24790..866132d3 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
@@ -1 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# /tmp/go-build472300524/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+
DRAM Part Name ID to assign
+K3KL8L80CM-MGCT 0 (0000)
+K3KL6L60GM-MGCT 1 (0001)
+H58G56AK6BX069 2 (0010)
+H9JCNNNBK3MLYR-N6E 3 (0011)
diff --git a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
index 2499005..deeb000 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
@@ -9,3 +9,7 @@
# See util/spd_tools/README.md for more details and instructions.
# Part Name
+K3KL8L80CM-MGCT
+K3KL6L60GM-MGCT
+H58G56AK6BX069
+H9JCNNNBK3MLYR-N6E
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 17:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80343/comment/135bcdb3_51541d1b :
PS15, Line 33: - SATA ACPI error
> Could you rebase on main and try again? CB:80554 probably fixes the issue.
Awesome! The message disappeared. 😊
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80411?usp=email
to look at the new patch set (#15).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s
......................................................................
Documentation/mainboard/lenovo: Add ThinkCentre M710s
Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/ch341a_pinout.jpg
A Documentation/mainboard/lenovo/thinkcentre_m710s.md
A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg
4 files changed, 207 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80411/15
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Hello Alexander Couzens, Felix Singer, Nico Huber, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80343?usp=email
to look at the new patch set (#17).
Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
mainboard/lenovo: Add ThinkCentre M710s (Skylake)
The processor may be a Pentium or 6/7th generation Core i3/i5/i7.
This port was tested on an i5-7400.
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing
- PEG
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (output)
- COM1
- TPM
Not Working:
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Untested:
- Audio (input)
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
A src/mainboard/lenovo/thinkcentre_m710s/data.vbt
A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
A src/mainboard/lenovo/thinkcentre_m710s/gpio.h
A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
A src/mainboard/lenovo/thinkcentre_m710s/ramstage.c
A src/mainboard/lenovo/thinkcentre_m710s/romstage.c
15 files changed, 700 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/17
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email )
Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 16:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80343/comment/66593298_fe1d4051 :
PS15, Line 33: - SATA ACPI error
> ``` […]
Could you rebase on main and try again? CB:80554 probably fixes the issue.
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 16:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80343/comment/f35c368e_0444d418 :
PS15, Line 33: - SATA ACPI error
> Could you paste a log snippet for that?
```
ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.SATA], AE_NOT_FOUND (20230331/dswload2-162)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230331/psobject-220)
```
It does not affect general use, so I haven't looked into it.
File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80343/comment/63dee91d_6cdc3cd0 :
PS15, Line 46: register "SataMode" = "SATA_AHCI"
> AHCI is the default, remove.
Done
File src/mainboard/lenovo/thinkcentre_m710s/romstage.c:
https://review.coreboot.org/c/coreboot/+/80343/comment/cada8668_921494b6 :
PS15, Line 10: const u16 rcomp_resistors[] = {121, 75, 100};
: const u16 rcomp_targets[] = {60, 26, 20, 20, 26};
> nit: could be put within mainboard_memory_init_params() as they are memcpy'd anyway.
Done
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Hello Alexander Couzens, Felix Singer, Nico Huber, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80343?usp=email
to look at the new patch set (#16).
The following approvals got outdated and were removed:
Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
mainboard/lenovo: Add ThinkCentre M710s (Skylake)
The processor may be a Pentium or 6/7th generation Core i3/i5/i7.
This port was tested on an i5-7400.
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing
- PEG
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (output)
- COM1
- TPM
Not Working:
- SATA ACPI error
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Untested:
- Audio (input)
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
A src/mainboard/lenovo/thinkcentre_m710s/data.vbt
A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
A src/mainboard/lenovo/thinkcentre_m710s/gpio.h
A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
A src/mainboard/lenovo/thinkcentre_m710s/ramstage.c
A src/mainboard/lenovo/thinkcentre_m710s/romstage.c
15 files changed, 700 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/16
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80636?usp=email )
Change subject: mb/google/brya: Create glassway variant
......................................................................
mb/google/brya: Create glassway variant
Create the glassway variant of the nivviks reference board by copying
the template files to a new directory named for the variant.
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=None
Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c
Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80636
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/glassway/include/variant/ec.h
A src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
A src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
A src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/glassway/overridetree.cb
8 files changed, 48 insertions(+), 0 deletions(-)
Approvals:
Kapil Porwal: Looks good to me, approved
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
Daniel Peng: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 4a38af5..eb937523 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -234,6 +234,9 @@
select INTEL_GMA_HAVE_VBT
select SOC_INTEL_RAPTORLAKE
+config BOARD_GOOGLE_GLASSWAY
+ select BOARD_GOOGLE_BASEBOARD_NISSA
+
config BOARD_GOOGLE_GOTHRAX
select BOARD_GOOGLE_BASEBOARD_NISSA
select DRIVERS_GENERIC_GPIO_KEYS
@@ -590,6 +593,7 @@
default 0x0 if BOARD_GOOGLE_QUANDISO
default 0x0 if BOARD_GOOGLE_ANRAGGAR
default 0x1 if BOARD_GOOGLE_XOL
+ default 0x0 if BOARD_GOOGLE_GLASSWAY
config DRIVER_TPM_I2C_ADDR
hex
@@ -673,6 +677,7 @@
default "Dochi" if BOARD_GOOGLE_DOCHI
default "Anraggar" if BOARD_GOOGLE_ANRAGGAR
default "Xol" if BOARD_GOOGLE_XOL
+ default "Glassway" if BOARD_GOOGLE_GLASSWAY
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -727,6 +732,7 @@
default "dochi" if BOARD_GOOGLE_DOCHI
default "anraggar" if BOARD_GOOGLE_ANRAGGAR
default "xol" if BOARD_GOOGLE_XOL
+ default "glassway" if BOARD_GOOGLE_GLASSWAY
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index 4371597..bea92b6 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -56,6 +56,9 @@
config BOARD_GOOGLE_GLADIOS
bool "-> Gladios"
+config BOARD_GOOGLE_GLASSWAY
+ bool "-> Glassway"
+
config BOARD_GOOGLE_GOTHRAX
bool "-> Gothrax"
diff --git a/src/mainboard/google/brya/variants/glassway/include/variant/ec.h b/src/mainboard/google/brya/variants/glassway/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
new file mode 100644
index 0000000..2499005
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I597666a5be6f71b82c7baddbe343da3d5117dd1c
Gerrit-Change-Number: 80636
Gerrit-PatchSet: 2
Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>
Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Gerrit-MessageType: merged