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Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
Patch Set 6:
(5 comments)
File src/mainboard/lenovo/m900_tiny/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80610/comment/d45b8914_3ecd7a68 :
PS6, Line 7: register "deep_s3_enable_ac" = "0"
: r
Remove
https://review.coreboot.org/c/coreboot/+/80610/comment/652d7719_492841da :
PS6, Line 23: register "PrimaryDisplay" = "Display_iGFX"
Move into the igpu scope.
https://review.coreboot.org/c/coreboot/+/80610/comment/12852594_04bc2b0e :
PS6, Line 162: [5] = 0,
Remove
https://review.coreboot.org/c/coreboot/+/80610/comment/642fc987_5d88ef39 :
PS6, Line 167: [2] = 0,
: [3] = 0,
: [4] = 0,
:
Disabled, remove
https://review.coreboot.org/c/coreboot/+/80610/comment/3003b870_efb31e1c :
PS6, Line 234: device ref p2sb on end
:
These are enabled in the chipset devicetree. Remove.
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Change subject: mb/google/nissa/var/glassway: Generate SPD ID for supported memory parts
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add fsp_headers.h
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> still need to polish to make CPX pass, stay tuned.
Please mark patches as WIP if they are not ready for review.
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The following approvals got outdated and were removed:
Code-Review-1 by Shuo Liu
Change subject: soc/intel/xeon_sp: Add fsp_headers.h
......................................................................
soc/intel/xeon_sp: Add fsp_headers.h
FSP headers change across SoC generations. Add fsp_headers.h as
the centralized placeholder to include these headers and related
definitions for Xeon-SP common codes, thus to reduce this
dependency.
TEST=intel/archercity CRB
Change-Id: I89a87ec72933484326cb594b83bb3ed39d06b85c
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
---
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
A src/soc/intel/xeon_sp/include/soc/fsp_headers.h
D src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/ioat.c
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_iiouds.h
9 files changed, 37 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/80684/3
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Change subject: soc/intel/xeon_sp: Add fsp_headers.h
......................................................................
Patch Set 2: Code-Review-1
(1 comment)
Patchset:
PS2:
still need to polish to make CPX pass, stay tuned.
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80684?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp: Add fsp_headers.h
......................................................................
soc/intel/xeon_sp: Add fsp_headers.h
FSP headers change across SoC generations. Add fsp_headers.h as
the centralized placeholder to include these headers and related
definitions for Xeon-SP common codes, thus to reduce this
dependency.
TEST=intel/archercity CRB
Change-Id: I89a87ec72933484326cb594b83bb3ed39d06b85c
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
---
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/include/soc/fsp_headers.h
D src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/spr/ioat.c
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_iiouds.h
8 files changed, 36 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/80684/2
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