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Change subject: i2c/drivers/generic: Add support for including a rotation matrix
......................................................................
Patch Set 6:
(1 comment)
File src/drivers/i2c/generic/chip.h:
https://review.coreboot.org/c/coreboot/+/80179/comment/69f9c0e9_5a843777 :
PS4, Line 81: int
> no, i'd use bool for has_rotation_matrix righ taway and change the other ones in a follow-up
Done
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Change subject: soc/intel/xeon_sp: Add fsp_headers.h
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Please mark patches as WIP if they are not ready for review.
Sure, should I add a note in the commit message?
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Change subject: superio/ite: Add IT8629E
......................................................................
Patch Set 9:
(1 comment)
File src/superio/ite/it8629e/Kconfig:
https://review.coreboot.org/c/coreboot/+/80344/comment/698bb1c1_750ee0cb :
PS9, Line 3: # Unfortunately, the datasheet for IT8629E is not public . Therefore, we will
: # use the functionally closest chip (i.e. IT8728F) as a reference and try to
: # reverse-engineer where necessary.
:
: # IT8629E seems to be very similar to IT8628E (again, no public datasheets), as
: # the chip id is 0x8628.
Please remove that from here and add it to the commit message. Do you know of any differences? If so, please document that as well.
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/80343/comment/99eb3c01_97974577 :
PS8, Line 20: AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
> There was Intel HDMI/DP here (https://review.coreboot.org/c/coreboot/+/80343/4.. […]
Yes, please bring the pin configurations back.
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Change subject: [test only] upgrade to gcc-14-20240211
......................................................................
Patch Set 4:
(1 comment)
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/80607/comment/e11feef1_98b33d92 :
PS4, Line 73: GCC_BASE_URL="https://gcc.gnu.org/pub/gcc/snapshots/LATEST-14"
A new snapshot is available and the latest pointer changed. I suggest to use these paths https://gcc.gnu.org/pub/gcc/snapshots/14-20240211/
For the new snapshot: https://gcc.gnu.org/pub/gcc/snapshots/14-20240218/
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Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/lenovo/m900_tiny/bootblock.c:
https://review.coreboot.org/c/coreboot/+/80610/comment/9ad88924_fb2e5db9 :
PS6, Line 13: void bootblock_mainboard_init(void)
: {
: mainboard_configure_early_gpios();
: }
Why is that needed? bootblock_mainboard_early_init() should work fine.
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Change subject: mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)
......................................................................
Patch Set 6:
(4 comments)
File src/mainboard/lenovo/m900_tiny/Kconfig:
https://review.coreboot.org/c/coreboot/+/80610/comment/bc15c2f1_8b151ec7 :
PS6, Line 25: int
Remove, avoid type redefinitions.
https://review.coreboot.org/c/coreboot/+/80610/comment/d9eafa9f_52e484ef :
PS6, Line 36: hex
Remove, avoid type redefinitions.
File src/mainboard/lenovo/m900_tiny/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80610/comment/93a34d68_faa7c5b5 :
PS6, Line 173: device ref uart2 off end # LPSS UART - pins 17, 18 on GXDP header on board underside
Please don't add disabled devices to the devicetree. Document the pins in the commit message.
File src/mainboard/lenovo/m900_tiny/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/80610/comment/276e8c98_16fa216c :
PS6, Line 10: // OEM revision
Seems superfluous, remove.
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Elyes Haouas has uploaded a new patch set (#7). ( https://review.coreboot.org/c/coreboot/+/80649?usp=email )
Change subject: (test) Remove google/oak to update chromeec submodule
......................................................................
(test) Remove google/oak to update chromeec submodule
Change-Id: Ie5b22057f52d66c1334d5ddcbd516e352a861441
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
D src/mainboard/google/oak/Kconfig
D src/mainboard/google/oak/Kconfig.name
D src/mainboard/google/oak/Makefile.mk
D src/mainboard/google/oak/board_info.txt
D src/mainboard/google/oak/boardid.c
D src/mainboard/google/oak/bootblock.c
D src/mainboard/google/oak/chromeos.c
D src/mainboard/google/oak/chromeos.fmd
D src/mainboard/google/oak/devicetree.cb
D src/mainboard/google/oak/gpio.h
D src/mainboard/google/oak/mainboard.c
D src/mainboard/google/oak/romstage.c
D src/mainboard/google/oak/sdram_configs.c
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-H9CCNNNBJTALAR-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-H9CCNNNBLTBLAR-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EB-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EC-EGCG-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304EE-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304EE-2GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E324EB-2GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-lpddr3-NT6CL512T32AM-H0-4GB.inc
D src/mainboard/google/oak/sdram_inf/sdram-unused.inc
D src/mainboard/google/oak/tpm_tis.c
27 files changed, 0 insertions(+), 2,085 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/80649/7
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