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[M] Change in coreboot[main]: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
by Felix Held (Code Review) 13 Feb '24

13 Feb '24

Attention is currently required from: Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80464?usp=email ) Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ ...................................................................... Patch Set 1: (1 comment) File src/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/80464/comment/6dbae7d6_a35674a6 : PS1, Line 101: ACPI_PCI_ROOT_RESOURCE_PRODUCER not sure if there might be a better name for this. can't say that i'm 100% happy with this name, but couldn't think of anything that's substantially better and not even more verbose -- To view, visit https://review.coreboot.org/c/coreboot/+/80464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Gerrit-Change-Number: 80464 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 13 Feb 2024 00:44:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
by Felix Held (Code Review) 13 Feb '24

13 Feb '24

Attention is currently required from: Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80464?usp=email ) Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: was talking with Patrick about making that function common which will probably be quite useful for some non-AMD SoCs too -- To view, visit https://review.coreboot.org/c/coreboot/+/80464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Gerrit-Change-Number: 80464 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 13 Feb 2024 00:41:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
by Felix Held (Code Review) 13 Feb '24

13 Feb '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80464?usp=email ) Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ ...................................................................... soc/amd: move common pci_domain_fill_ssdt implementation to acpi/ Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt implementation doesn't contain any AMD-specific code and can also be used by other SoCs. So factor it out, move the implementation to src/acpi/acpigen_pci_root_resource_producer.c, and rename it to pci_domain_fill_ssdt. When a SoC now selects ACPI_PCI_ROOT_RESOURCE_PRODUCER, it can assign pci_domain_fill_ssdt to its domain operation's acpi_fill_ssdt function pointer to have the PCI domain resource producer information added to its SSDT. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 --- M src/acpi/Kconfig M src/acpi/Makefile.mk A src/acpi/acpigen_pci_root_resource_producer.c M src/include/acpi/acpigen_pci.h M src/soc/amd/cezanne/chip.c M src/soc/amd/common/block/data_fabric/Kconfig M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c 13 files changed, 133 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80464/1 diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 417ff60..0425442 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -98,6 +98,17 @@ help Set the maximum size of all ACPI tables in KiB. +config ACPI_PCI_ROOT_RESOURCE_PRODUCER + bool + depends on HAVE_ACPI_TABLES && PCI + help + Add a common pci_domain_fill_ssdt implementation to the build that + generates the SSDT entries for the bus numbers, resource producers, + bus number, and domain number of a PCI root. This code requires the + domain's scan_bus function to have reported the correct PCI bus range + and segment group, and the dmoain's read_resources function to have + reported the correct IO and MMIO resource producer regions. + config ACPI_PPTT bool depends on HAVE_ACPI_TABLES diff --git a/src/acpi/Makefile.mk b/src/acpi/Makefile.mk index 6bb34cb..2114577 100644 --- a/src/acpi/Makefile.mk +++ b/src/acpi/Makefile.mk @@ -7,6 +7,7 @@ ramstage-y += acpi_apic.c ramstage-y += acpi_dmar.c ramstage-y += acpi_hpet.c +ramstage-$(CONFIG_ACPI_PCI_ROOT_RESOURCE_PRODUCER) += acpigen_pci_root_resource_producer.c endif ramstage-$(CONFIG_ACPI_PPTT) += acpi_pptt.c ramstage-y += acpigen.c diff --git a/src/acpi/acpigen_pci_root_resource_producer.c b/src/acpi/acpigen_pci_root_resource_producer.c new file mode 100644 index 0000000..c9efe0e --- /dev/null +++ b/src/acpi/acpigen_pci_root_resource_producer.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> +#include <arch/pci_io_cfg.h> +#include <arch/vga.h> +#include <console/console.h> +#include <device/device.h> +#include <types.h> + +static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, + resource_t base, resource_t limit) +{ + printk(BIOS_DEBUG, "%s _CRS: adding IO range [%llx-%llx]\n", domain_name, base, limit); + acpigen_resource_producer_io(base, limit); +} + +static void write_ssdt_domain_io_producer_range(const char *domain_name, + resource_t base, resource_t limit) +{ + /* + * Split the IO region at the PCI config IO ports so that the IO resource producer + * won't cover the same IO ports that the IO resource consumer for the PCI config IO + * ports in the same ACPI device already covers. + */ + if (base < PCI_IO_CONFIG_INDEX) { + write_ssdt_domain_io_producer_range_helper(domain_name, + base, + MIN(limit, PCI_IO_CONFIG_INDEX - 1)); + } + if (limit > PCI_IO_CONFIG_LAST_PORT) { + write_ssdt_domain_io_producer_range_helper(domain_name, + MAX(base, PCI_IO_CONFIG_LAST_PORT + 1), + limit); + } +} + +static void write_ssdt_domain_mmio_producer_range(const char *domain_name, + resource_t base, resource_t limit) +{ + printk(BIOS_DEBUG, "%s _CRS: adding MMIO range [%llx-%llx]\n", + domain_name, base, limit); + acpigen_resource_producer_mmio(base, limit, + MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE); +} + +void pci_domain_fill_ssdt(const struct device *domain) +{ + const char *acpi_scope = acpi_device_path(domain); + printk(BIOS_DEBUG, "%s ACPI scope: '%s'\n", __func__, acpi_scope); + acpigen_write_scope(acpi_device_path(domain)); + + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + + /* PCI bus number range in domain */ + printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n", + acpi_device_name(domain), domain->downstream->secondary, + domain->downstream->max_subordinate, domain->downstream->segment_group); + acpigen_resource_producer_bus_number(domain->downstream->secondary, + domain->downstream->max_subordinate); + + if (domain->path.domain.domain == 0) { + /* ACPI 6.4.2.5 I/O Port Descriptor */ + acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, + PCI_IO_CONFIG_PORT_COUNT, 1); + } + + struct resource *res; + for (res = domain->resource_list; res != NULL; res = res->next) { + if (!(res->flags & IORESOURCE_ASSIGNED)) + continue; + /* Don't add MMIO producer ranges for reserved MMIO regions from non-PCI + devices */ + if (res->flags & IORESOURCE_RESERVE) + continue; + /* Don't add MMIO producer ranges for DRAM regions */ + if (res->flags & IORESOURCE_STORED) + continue; + switch (res->flags & IORESOURCE_TYPE_MASK) { + case IORESOURCE_IO: + write_ssdt_domain_io_producer_range(acpi_device_name(domain), + res->base, res->limit); + break; + case IORESOURCE_MEM: + write_ssdt_domain_mmio_producer_range(acpi_device_name(domain), + res->base, res->limit); + break; + default: + break; + } + } + + if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); + acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, + MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); + } + + acpigen_write_resourcetemplate_footer(); + + acpigen_write_SEG(domain->downstream->segment_group); + acpigen_write_BBN(domain->downstream->secondary); + /* Scope */ + acpigen_pop_len(); +} diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h index 8a96eb3..69216ec 100644 --- a/src/include/acpi/acpigen_pci.h +++ b/src/include/acpi/acpigen_pci.h @@ -14,4 +14,6 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, const char *source_path, unsigned int index); +void pci_domain_fill_ssdt(const struct device *domain); + #endif /* ACPIGEN_PCI_H */ diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 83fd5c6..7463352 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -32,7 +33,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/common/block/data_fabric/Kconfig b/src/soc/amd/common/block/data_fabric/Kconfig index add2374..bae4bed 100644 --- a/src/soc/amd/common/block/data_fabric/Kconfig +++ b/src/soc/amd/common/block/data_fabric/Kconfig @@ -7,6 +7,7 @@ config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN bool depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select ACPI_PCI_ROOT_RESOURCE_PRODUCER select SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX help Select this option to add functionality to the build to tell the diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index ab85e2b5..b056d60 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -1,10 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> #include <amdblocks/data_fabric.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> #include <console/console.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> @@ -214,100 +212,3 @@ read_soc_memmap_resources(domain, &idx); } } - -static void write_ssdt_domain_io_producer_range_helper(const char *domain_name, - resource_t base, resource_t limit) -{ - printk(BIOS_DEBUG, "%s _CRS: adding IO range [%llx-%llx]\n", domain_name, base, limit); - acpigen_resource_producer_io(base, limit); -} - -static void write_ssdt_domain_io_producer_range(const char *domain_name, - resource_t base, resource_t limit) -{ - /* - * Split the IO region at the PCI config IO ports so that the IO resource producer - * won't cover the same IO ports that the IO resource consumer for the PCI config IO - * ports in the same ACPI device already covers. - */ - if (base < PCI_IO_CONFIG_INDEX) { - write_ssdt_domain_io_producer_range_helper(domain_name, - base, - MIN(limit, PCI_IO_CONFIG_INDEX - 1)); - } - if (limit > PCI_IO_CONFIG_LAST_PORT) { - write_ssdt_domain_io_producer_range_helper(domain_name, - MAX(base, PCI_IO_CONFIG_LAST_PORT + 1), - limit); - } -} - -static void write_ssdt_domain_mmio_producer_range(const char *domain_name, - resource_t base, resource_t limit) -{ - printk(BIOS_DEBUG, "%s _CRS: adding MMIO range [%llx-%llx]\n", - domain_name, base, limit); - acpigen_resource_producer_mmio(base, limit, - MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE); -} - -void amd_pci_domain_fill_ssdt(const struct device *domain) -{ - const char *acpi_scope = acpi_device_path(domain); - printk(BIOS_DEBUG, "%s ACPI scope: '%s'\n", __func__, acpi_scope); - acpigen_write_scope(acpi_device_path(domain)); - - acpigen_write_name("_CRS"); - acpigen_write_resourcetemplate_header(); - - /* PCI bus number range in domain */ - printk(BIOS_DEBUG, "%s _CRS: adding busses [%x-%x] in segment group %x\n", - acpi_device_name(domain), domain->downstream->secondary, - domain->downstream->max_subordinate, domain->downstream->segment_group); - acpigen_resource_producer_bus_number(domain->downstream->secondary, - domain->downstream->max_subordinate); - - if (domain->path.domain.domain == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, - PCI_IO_CONFIG_PORT_COUNT, 1); - } - - struct resource *res; - for (res = domain->resource_list; res != NULL; res = res->next) { - if (!(res->flags & IORESOURCE_ASSIGNED)) - continue; - /* Don't add MMIO producer ranges for reserved MMIO regions from non-PCI - devices */ - if (res->flags & IORESOURCE_RESERVE) - continue; - /* Don't add MMIO producer ranges for DRAM regions */ - if (res->flags & IORESOURCE_STORED) - continue; - switch (res->flags & IORESOURCE_TYPE_MASK) { - case IORESOURCE_IO: - write_ssdt_domain_io_producer_range(acpi_device_name(domain), - res->base, res->limit); - break; - case IORESOURCE_MEM: - write_ssdt_domain_mmio_producer_range(acpi_device_name(domain), - res->base, res->limit); - break; - default: - break; - } - } - - if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_DEBUG, "%s _CRS: adding VGA resource\n", acpi_device_name(domain)); - acpigen_resource_producer_mmio(VGA_MMIO_BASE, VGA_MMIO_LIMIT, - MEM_RSRC_FLAG_MEM_READ_WRITE | MEM_RSRC_FLAG_MEM_ATTR_CACHE); - } - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_SEG(domain->downstream->segment_group); - acpigen_write_BBN(domain->downstream->secondary); - /* Scope */ - acpigen_pop_len(); -} diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index f0073df..fbed0b2 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -55,6 +55,4 @@ void amd_pci_domain_read_resources(struct device *domain); void amd_pci_domain_scan_bus(struct device *domain); -void amd_pci_domain_fill_ssdt(const struct device *domain); - #endif /* AMD_BLOCK_DATA_FABRIC_H */ diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 14248cd..5672f65 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/ioapic.h> #include <amdblocks/data_fabric.h> #include <amdblocks/root_complex.h> @@ -63,5 +64,5 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = genoa_domain_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index 515580d..e227f41 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -2,6 +2,7 @@ /* TODO: Update for Glinda */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -34,7 +35,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 729f97a..fb61f585 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -32,7 +33,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index f45e7b8..a88468b 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -2,6 +2,7 @@ /* TODO: Update for Phoenix */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -35,7 +36,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 7411948..e642060 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_pci.h> #include <amdblocks/acpi.h> #include <amdblocks/data_fabric.h> #include <amdblocks/fsp.h> @@ -33,7 +34,7 @@ .scan_bus = amd_pci_domain_scan_bus, .init = amd_pci_domain_init, .acpi_name = soc_acpi_name, - .acpi_fill_ssdt = amd_pci_domain_fill_ssdt, + .acpi_fill_ssdt = pci_domain_fill_ssdt, }; static void soc_init(void *chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/80464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Gerrit-Change-Number: 80464 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/qemu/fw_cfg: Support using DMA to select fw_cfg file
by Paul Menzel (Code Review) 13 Feb '24

13 Feb '24

Attention is currently required from: Alper Nebi Yasak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80365?usp=email ) Change subject: mb/qemu/fw_cfg: Support using DMA to select fw_cfg file ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80365/comment/570c31be_eba28431 : PS1, Line 15: to other architectures Only qemu-i440fx is changed though. Is its file used for all QEMU boards? -- To view, visit https://review.coreboot.org/c/coreboot/+/80365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46f9915e6df04d371c7084815f16034c7e9879d4 Gerrit-Change-Number: 80365 Gerrit-PatchSet: 1 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Comment-Date: Mon, 12 Feb 2024 23:20:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: superio/ite: Add IT8629E
by Paul Menzel (Code Review) 13 Feb '24

13 Feb '24

Attention is currently required from: Nicholas Sudsgaard. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80344?usp=email ) Change subject: superio/ite: Add IT8629E ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80344?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44d0377da11f0e118017caa4357012df9373b322 Gerrit-Change-Number: 80344 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Mon, 12 Feb 2024 23:18:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/mtl: Increase the IgdDvmt50PreAlloc UPD size to 128MB
by Paul Menzel (Code Review) 12 Feb '24

12 Feb '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, sridhar siricilla. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80406?usp=email ) Change subject: soc/intel/mtl: Increase the IgdDvmt50PreAlloc UPD size to 128MB ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80406/comment/6432f6c7_55ea85e3 : PS8, Line 7: Increase “Double” would be even more specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/80406?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618 Gerrit-Change-Number: 80406 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: sridhar siricilla <siricillasridhar(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 12 Feb 2024 22:49:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMC
by Paul Menzel (Code Review) 12 Feb '24

12 Feb '24

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80315?usp=email ) Change subject: soc/mediatek/mt8188: Enable CROS_WIDEVINE_SMC ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80315/comment/d1f9fd09_6ef09b5e : PS3, Line 8: Please elaborate next time. -- To view, visit https://review.coreboot.org/c/coreboot/+/80315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dded9042abd85a948598f98475c21a1af9b4d80 Gerrit-Change-Number: 80315 Gerrit-PatchSet: 3 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 12 Feb 2024 22:48:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: tree; Remove unused <lib.h>
by Paul Menzel (Code Review) 12 Feb '24

12 Feb '24

Attention is currently required from: Andrey Petrov, Elyes Haouas, Ronak Kanabar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80433?usp=email ) Change subject: tree; Remove unused <lib.h> ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa5c89aad7d0538c556665f8b4372e44cf593822 Gerrit-Change-Number: 80433 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 12 Feb 2024 22:47:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/tigerlake: Drop redundant PcieRpEnable
by Nico Huber (Code Review) 12 Feb '24

12 Feb '24

Attention is currently required from: Arthur Heymans, Jeremy Compostella, Jeremy Soller, Michael Niewöhner, Nick Vaccaro, Nico Huber, Subrata Banik, Tim Crawford. Hello Arthur Heymans, Jeremy Compostella, Jeremy Soller, Michael Niewöhner, Nicholas Sudsgaard, Nick Vaccaro, Subrata Banik, Tim Crawford, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79920?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/tigerlake: Drop redundant PcieRpEnable ...................................................................... soc/intel/tigerlake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/soc/intel/tigerlake/Makefile.mk M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 16 files changed, 20 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79920/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Gerrit-Change-Number: 79920 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/jasperlake: Drop redundant PcieRpEnable
by Jonathon Hall (Code Review) 12 Feb '24

12 Feb '24

Attention is currently required from: Arthur Heymans, Jeremy Compostella, Nico Huber. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79919?usp=email ) Change subject: soc/intel/jasperlake: Drop redundant PcieRpEnable ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79919?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Gerrit-Change-Number: 79919 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 12 Feb 2024 22:20:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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