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Change subject: [UNTESTED]nb/intel/gm45: Use ssdt PCI root bridge generator
......................................................................
Patch Set 3:
(1 comment)
File src/northbridge/intel/gm45/northbridge.c:
https://review.coreboot.org/c/coreboot/+/80465/comment/65263bb3_fea5f68f :
PS3, Line 111: struct resource *upper_pci = find_resource(dev, IOINDEX_SUBTRACTIVE(2, 0));
: if (upper_pci)
: upper_pci->base = touud;
:
: struct resource *lower_pci = find_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
: if (lower_pci)
: lower_pci->base = tolud;
> It might be less confusing to just declare the bridge resources locally rather than patching them up […]
+1
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Change subject: device/pci_device.c: Avoid adding invalid resources
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Does it fix a real problem, though? It's not uncommon to have `limit < base` for
> an empty resource.
Not currently, however CB:80464 does not seem to check for that.
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Change subject: device/pci_device.c: Avoid adding invalid resources
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Does it fix a real problem, though? It's not uncommon to have `limit < base` for
an empty resource.
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Change subject: [UNTESTED]nb/intel/gm45: Use ssdt PCI root bridge generator
......................................................................
Patch Set 3:
(1 comment)
File src/northbridge/intel/gm45/northbridge.c:
https://review.coreboot.org/c/coreboot/+/80465/comment/1f4a90d8_4451a41d :
PS3, Line 111: struct resource *upper_pci = find_resource(dev, IOINDEX_SUBTRACTIVE(2, 0));
: if (upper_pci)
: upper_pci->base = touud;
:
: struct resource *lower_pci = find_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
: if (lower_pci)
: lower_pci->base = tolud;
It might be less confusing to just declare the bridge resources locally rather than patching them up from the default implementation.
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Arthur Heymans has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/80465?usp=email )
Change subject: [UNTESTED]nb/intel/gm45: Use ssdt PCI root bridge generator
......................................................................
[UNTESTED]nb/intel/gm45: Use ssdt PCI root bridge generator
This drops the ACPI oprom, legacy bios regions and TPM from ACPI. It's
unclear whether those matter.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ic558359101c59d6137a0abb460d19feeda36c6dc
---
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/acpi/hostbridge.asl
M src/northbridge/intel/gm45/northbridge.c
3 files changed, 11 insertions(+), 175 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/80465/3
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Change subject: mb/amd/birman: Add Birmanplus board support for PHX1 SOC
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> did you verify that the soc's gpio configuration in gpio.c and the ec's gpio configuration in ec. […]
we are mostly using the Birman's EC GPIOs. I will address some differences in a separate PR.
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun, build bot (Jenkins), sridhar siricilla,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80406?usp=email
to look at the new patch set (#9).
Change subject: soc/intel/mtl: Double the `IgdDvmt50PreAlloc` UPD size to 128MB
......................................................................
soc/intel/mtl: Double the `IgdDvmt50PreAlloc` UPD size to 128MB
This patch increases the IgdDvmt50PreAlloc value as per Intel
recommendation starting with GFX PEIM 103x.
TEST=Able to build and boot google/rex.
Change-Id: I236b38a1ac5efbfcd23e373c09204d8a07b97618
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/romstage/fsp_params.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/80406/9
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