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Change subject: soc/intel/jasperlake: Drop redundant PcieRpEnable
......................................................................
soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/baseboard/ramstage.c
M src/mainboard/google/dedede/variants/boxy/overridetree.cb
M src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
M src/mainboard/google/dedede/variants/dexi/overridetree.cb
M src/mainboard/google/dedede/variants/dibbi/overridetree.cb
M src/mainboard/google/dedede/variants/dita/overridetree.cb
M src/mainboard/google/dedede/variants/sasuke/overridetree.cb
M src/mainboard/google/dedede/variants/sasukette/overridetree.cb
M src/mainboard/google/dedede/variants/storo/overridetree.cb
M src/mainboard/google/dedede/variants/taranza/overridetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
M src/mainboard/purism/librem_jsl/devicetree.cb
M src/soc/intel/jasperlake/Makefile.mk
M src/soc/intel/jasperlake/chip.c
M src/soc/intel/jasperlake/chip.h
A src/soc/intel/jasperlake/include/soc/pcie.h
A src/soc/intel/jasperlake/pcie_rp.c
M src/soc/intel/jasperlake/romstage/fsp_params.c
19 files changed, 41 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79919/3
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Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
Patch Set 19:
(1 comment)
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/77338/comment/29e42c48_f4c50ffe :
PS18, Line 653: pciexp_dev_set_max_payload_size(parent, max_payload);
> Would it make sense to put this inside `if` below?
Agreed. It would save a few cycles without making the code more complicated.
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Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
Patch Set 19: Code-Review+1
(2 comments)
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/77338/comment/b0187717_efe5701a :
PS18, Line 596: unsigned int
> All `pci_find_capability(dev, PCI_CAP_ID_PCIE);` calls were assigning a value to unsigned int (with […]
I have no strong preference. Though, in general, limiting the type also constraints
the compiler in the choices of optimizations it can make. So `unsigned int` seems
fine as long as there is no benefit to a human reader when using a fixed-width
type (I see none, but can only speak for myself).
https://review.coreboot.org/c/coreboot/+/77338/comment/1b88f28b_c2ba7180 :
PS18, Line 721: parent's
> Shouldn't the root's (real one, not what `root` variable points to) Max Payload Size be limited here […]
pciexp_scan_bus() should be called for the next pair of parent and child after
the loop below (line 760) is done with the current level. That should propagate
it further up to the root port. pciexp_sync_max_payload_size() should only run on
the upper-most level after *all* calls to pciexp_scan_bus() below a given root
port are done.
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Change subject: security/tpm: make tis_probe() return tpm_family
......................................................................
Patch Set 23:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69159/comment/9b524498_1685a88c :
PS23, Line 9:
> Nit: double space
Edited, but it's not a typo, I just prefer two spaces between sentences to differentiate end of sentence from other uses of dots: https://en.wikipedia.org/wiki/Sentence_spacing
File src/drivers/i2c/tpm/tpm.h:
https://review.coreboot.org/c/coreboot/+/69159/comment/2df42aa0_bbd9d1e4 :
PS23, Line 17: #include <security/tpm/tis.h>
> alphabetical order.
Done
File src/drivers/i2c/tpm/tpm.c:
https://review.coreboot.org/c/coreboot/+/69159/comment/dfed1b97_e806d2c8 :
PS1, Line 461: *tpm_family = 1;
> It seems that this is the sanest way to go, but please add a comment explaining it above the lines w […]
Updated both `tpm.c` and `tis_atmel.c`.
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/69159/comment/65ff51a9_e6ed5bd8 :
PS23, Line 718: int
> This is no longer int.
Right, thanks.
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Hello Christian Walter, Cliff Huang, Julius Werner, Jérémy Compostella, Krystian Hebel, Lance Zhao, Michał Żygowski, Tim Wawrzynczak, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: security/tpm: replace CONFIG(TPMx) checks with runtime check
......................................................................
security/tpm: replace CONFIG(TPMx) checks with runtime check
This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2
during compilation, in which case actual TPM family in use can be
determined at runtime.
In some places both compile-time and runtime checks are necessary.
Yet in places like probe functions runtime state checks don't make sense
as runtime state is defined by results of probing.
Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/acpi/acpi.c
M src/drivers/crb/tis.c
M src/drivers/pc80/tpm/tis.c
M src/drivers/tpm/ppi.c
M src/security/tpm/tspi/crtm.h
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/vboot/secdata_tpm.c
M src/security/vboot/tpm_common.c
M src/vendorcode/google/chromeos/cse_board_reset.c
M src/vendorcode/google/chromeos/tpm2.c
11 files changed, 116 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69161/30
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Change subject: security/tpm: make tis_probe() return tpm_family
......................................................................
security/tpm: make tis_probe() return tpm_family
Via an out parameter. This is needed to be able to dynamically pick TSS
implementation based on the information discovered on probing.
Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/drivers/crb/tis.c
M src/drivers/i2c/tpm/cr50.c
M src/drivers/i2c/tpm/tis.c
M src/drivers/i2c/tpm/tis_atmel.c
M src/drivers/i2c/tpm/tpm.c
M src/drivers/i2c/tpm/tpm.h
M src/drivers/pc80/tpm/tis.c
M src/drivers/spi/tpm/tis.c
M src/security/tpm/tis.h
M src/security/tpm/tss/tcg-1.2/tss.c
M src/security/tpm/tss/tcg-2.0/tss.c
11 files changed, 86 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/69159/24
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Change subject: security/tpm: make tis_probe() return tpm_family
......................................................................
Patch Set 23:
(1 comment)
File src/drivers/i2c/tpm/tpm.h:
https://review.coreboot.org/c/coreboot/+/69159/comment/5e79e705_f48aa468 :
PS23, Line 17: #include <security/tpm/tis.h>
alphabetical order.
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Piotr Król has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80299?usp=email )
Change subject: mb/amd/birman: add Phoenix with openSIL mainboard option
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Felix, how does the Phoenix code name map to CPU models available on the market? From AMD website: https://www.amd.com/en/product/13036
7940HS is Phoenix. Will your introductory patches cover that CPU? Do you see any limitation regarding my mapping method between the code name and CPU model in light of future OpenSIL CPU support?
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80353?usp=email )
Change subject: mb/amd/birman: Add Birmanplus board support for PHX1 SOC
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80353/comment/c1628131_ef4e610e :
PS2, Line 9: 1)Initial commit for upstreaming Birmanplus mainboard changes.
> What does the *plus* mean?
birman+ is the name of this reference board
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