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Change subject: soc/intel/xeon_sp/util: Enhance lock_pam0123
......................................................................
soc/intel/xeon_sp/util: Enhance lock_pam0123
- Only compile code in ramstage
- Lock PAM on all sockets
- Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/util.c
4 files changed, 18 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/80101/11
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Change subject: soc/intel/xeon_sp: Drop unused MACROs
......................................................................
soc/intel/xeon_sp: Drop unused MACROs
Change-Id: I4067a1940f6cb3ee6d40c784877d7906495251a4
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
3 files changed, 1 insertion(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/80096/12
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Locate PCU by PCI device ID
......................................................................
soc/intel/xeon_sp: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Intel Document-ID: 735086
Intel Document-ID: 612246
Tested: On SPR 4S all PCU on all 4 sockets could be found and locked.
Change-Id: I06694715cba76b101165f1cef66d161b0f896b26
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/chip.c
M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
6 files changed, 107 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/80093/12
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80447?usp=email )
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Change subject: device/pciexp_device: Use 'PCI_BASE_ADDRESS_x' macros
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/80447/comment/6ddb1987_b7475d77 :
PS1, Line 711: PCI_BASE_ADDRESS_0
It's not a real PCI device, therefore noop_set_resources is used. The number for the resources used has no meaning (they don't refer to PCI config registers like real PCI device), and could have been 0, 1, 2 (in fact that's preferable to faking PCI BARs IMO). As a matter of fact it wouldn't even work if it were a real PCI device as the prefetch BAR needs an 8 byte BAR, not 4.
Using these macros is even more misleading than the raw numbers IMO.
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Change subject: mainboard: Enforce usage of AZALIA_ARRAY_SIZES
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/alderlake: Leverage IA common code for range calculations
......................................................................
Patch Set 9: Code-Review+2
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Change subject: soc/intel/cmn/sa: Add APIs into System Agent (SA) common code
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Patch Set 9: Code-Review+2
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Hello Alexander Couzens, Angel Pons, Stefan Ott,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mainboard: Enforce usage of AZALIA_ARRAY_SIZES
......................................................................
mainboard: Enforce usage of AZALIA_ARRAY_SIZES
This is the de facto method and should be enforced to keep things
consistent.
Change-Id: I7eee77f7fd49bc38e27cb0e6be0a4a6555098cc7
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/mainboard/acer/g43t-am3/hda_verb.c
M src/mainboard/amd/pademelon/hda_verb.c
M src/mainboard/asrock/g41c-gs/hda_verb.c
M src/mainboard/asus/p5qc/hda_verb.c
M src/mainboard/asus/p5ql-em/hda_verb.c
M src/mainboard/asus/p5qpl-am/hda_verb.c
M src/mainboard/foxconn/g41s-k/hda_verb.c
M src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
M src/mainboard/intel/dg41wv/hda_verb.c
M src/mainboard/intel/dg43gt/hda_verb.c
M src/mainboard/lenovo/thinkcentre_a58/hda_verb.c
11 files changed, 11 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/80422/3
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